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| 型號： | HC05PL4GRS |
| 英文描述： | 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification |
| 中文描述： | 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范 |
| 文件頁數(shù)： | 65/98頁 |
| 文件大小： | 1004K |
| 代理商： | HC05PL4GRS |
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April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
REV 2.0
8-BIT TIMER
MOTOROLA
10-3
T8EN - Timer8 Enable
This read/write bit enables the Timer8. Reset clears this bit.
1 =
Timer8 enabled
0 =
Timer8 disabled
PS2-PS0 - Prescaler select
These read/write bits is used to select the clock frequency to drive the 8-bit timer
counter. The counter will be driven by a internal bus clock (E-clock) through this
prescaler ratio. Upon reset and power on reset, the value of prescaler is set to a
default value of divided by 16.
10.3
TIMER8 COUNTER REGISTER (T8CNTR)
The T8CNTR is a read/write register which contains the current value of the 8-bit
timer counter. Reading this register enables the software to calculate the number
of internal and external clocks since the timer interrupt request flag (T8IF) was
set. Reading this address does not disturb the counter operation.
NOTE
This timer is used during the power-on sequence to time out the POR signal. The
timer is configured at power-on, with a prescaler division ratio of 16 and set to $FF
in Timer counter register. Also the clock source for the COP watchdog system is
derived from the output of this timer, hence a reset or preset of the prescaler and
timer counter register may affect the frequency of the watchdog timeout.
10.4
COMPUTER OPERATING PROPERLY (COP) WATCHDOG
Please refer to section on RESETS for details.
PS2
0
0
0
0
1
1
1
1
PS1
0
0
1
1
0
0
1
1
PS0
0
1
0
1
0
1
0
1
DIVIDE RATIO
1
2
4
8
16 (default after reset)
32
64
128
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
T8CNTR R
$000E
reset:
Timer 8 Counter Register
W
U
U
U
U
U
U
U
U
Figure 10-3. Timer8 Counter Register
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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