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參數(shù)資料
| 型號： | HC05PL4GRS |
| 英文描述： | 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification |
| 中文描述： | 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范 |
| 文件頁數(shù)： | 41/98頁 |
| 文件大?。?/td> | 1004K |
| 代理商： | HC05PL4GRS |
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April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
REV 2.0
OPERATING MODES
MOTOROLA
6-1
SECTION 6
OPERATING MODES
This section describes the various operating modes of the MC68HC05PL4.
6.1
OPERATING MODES
The MC68HC05PL4 has two operating modes: Single-Chip (Normal) Mode and
Self-Check Mode.
At the rising edge of the RESET, the device latches the states of LED/IRQ and
PB0/KBI0 pins and places itself in the specified mode. RESET must be held low
for the predefined power-on reset cycles of the internal PH2 clock after POR, or
for a time t
RL
for any other reset.
The conditions required to enter each mode are shown in
Table 6-1
. The mode of
operation is determined by the voltages on the LED/IRQ and PB0/KBI0 pins on
the rising edge of the external RESET pin.
6.1.1 Single-chip (Normal) Mode
The Single-Chip Mode is the normal operating mode, and it allows the device to
function as a self-contained microcontroller, with maximum use of the pins for on-
chip peripheral functions.
In the Single-Chip Mode all address and data activity occurs within the MCU and
is not available externally. Single-Chip Mode is entered if the LED/IRQ pin is within
the normal operating voltage range when the rising edge of a RESET occurs. In
Single-Chip Mode, all I/O port pins are available.
6.1.2 Self-check Mode
The self-check program is mask at location $1E00 to $1FEF, and is used for
checking device functionality under minimum hardware support.
Table 6-1. Operation Mode Condition After Reset
RESET Pin
LED/IRQ
PB0/KBI0
MODE
V
SS
to V
DD
V
SS
to V
DD
Single-Chip (Normal)
V
TST
V
DD
Self-Check
V
TST
= 2 x V
DD
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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