參數(shù)資料
型號(hào)： HC05PL4GRS
英文描述： 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification
中文描述： 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范
文件頁(yè)數(shù)： 61/98頁(yè)
文件大小： 1004K
代理商： HC05PL4GRS
April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
REV 2.0
16-BIT PROGRAMMABLE TIMER
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
9-11
9.7
16-BIT TIMER OPERATION DURING WAIT MODE
During WAIT mode the 16-bit timer continues to operate normally and may gener-
ate an interrupt to trigger the MCU out of the WAIT mode.
9.8
16-BIT TIMER OPERATION DURING STOP MODE
When the MCU enters the STOP mode the free-running counter stops counting
(the internal processor clock is stopped). It remains at that particular count value
until the STOP mode is exited by applying a low signal to the IRQ pin, at which
time the counter resumes from its stopped value as if nothing had happened. If
STOP mode is exited via an external reset (logic low applied to the RESET pin)
the counter is forced to timer interrupt vector.
If a valid input capture edge occurs at the PA2/TCAP pin during the STOP mode
the input capture detect circuitry will be armed. This action does not set any flags
or “wake up” the MCU, but when the MCU does “wake up” there will be an active
input capture flag (and data) from the first valid edge. If the STOP mode is exited
by an external reset, no input capture flag or data will be present even if a valid
input capture edge was detected during the STOP mode.
F
Freescale Semiconductor, Inc.
n
.
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