參數(shù)資料
型號： HC05PL4GRS
英文描述： 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification
中文描述： 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范
文件頁數(shù)： 30/98頁
文件大小： 1004K
代理商： HC05PL4GRS
GENERAL RELEASE SPECIFICATION
April 30, 1998
MOTOROLA
4-6
INTERRUPTS
MC68HC05PL4
REV 2.0
4.5
16-BIT TIMER INTERRUPTS
The 16-bit programmable Timer can generate an interrupt whenever the following
events occur:
Input capture
Output compare
Timer counter overflow
Setting the I bit in the condition code register disables Timer interrupts. The con-
trols for these interrupts are in the Timer control register (TCR) located at $0012
and in the status bits are in the Timer status register (TSR) located at $0013.
The 16-bit programmable Timer interrupts can wake up MCU from WAIT Mode.
4.5.1 Input Capture Interrupt
An input capture interrupt occurs if the input capture flag (ICF) becomes set while
the input capture interrupt enable bit (ICIE) is also set. The ICF flag bit is in the
TSR; and the ICIE enable bit is located in the MICSR. The ICF flag bit is cleared
by a read of the TSR with the ICF flag bit is set; and then followed by a read of the
LSB of the input capture register (ICRL) or by reset. The ICIE enable bit is unaf-
fected by reset.
4.5.2 Output Compare Interrupt
An output compare interrupt occurs if the output compare flag (OCF) becomes set
while the output compare interrupt enable bit (OCIE) is also set. The OCF flag bit
is in the TSR and the OCIE enable bit is in the MICSR. The OCF flag bit is cleared
by a read of the TSR with the OCF flag bit set; and then followed by an access to
the LSB of the output compare register (OCRL) or by reset. The OCIE enable bit is
unaffected by reset.
4.5.3 Timer Overflow Interrupt
A Timer overflow interrupt occurs if the Timer overflow flag (TOF) becomes set
while the Timer overflow interrupt enable bit (TOIE) is also set. The TOF flag bit is
in the TSR and the TOIE enable bit is in the TCR. The TOF flag bit is cleared by a
read of the TSR with the TOF flag bit set; and then followed by an access to the
LSB of the timer registers (TMRL) or by reset. The TOIE enable bit is unaffected
by reset.
4.6
8-BIT TIMER INTERRUPT
The 8-bit Timer can generate an interrupt when the Timer8 Counter Register
(T8CNTR) decrements from preset value to zero and the interrupt enable bit is
set. Setting the I bit in the condition code register disables this Timer interrupts.
The control bit for this interrupt and status bit are in the Timer 8 control register
(T8CSR) located at $000D.
The 8-Bit timer interrupt can wake up MCU from WAIT Mode.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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