
MC9S12DT128B Device User Guide — V01.07
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Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and
interrupts.
5.2 Vectors
5.2.1 Vector Table
Table 5-1
lists interrupt sources and vectors in default order of priority.
Table 5-1 Interrupt Vector Locations
Vector Address
Interrupt Source
CCR
Mask
None
None
None
None
None
X-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
Local Enable
HPRIO Value
to Elevate
–
–
–
–
–
–
$F2
$F0
$EE
$EC
$EA
$E8
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFEE, $FFEF
$FFEC, $FFED
$FFEA, $FFEB
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
Reset
None
Clock Monitor fail reset
COP failure reset
Unimplemented instruction trap
SWI
XIRQ / BF High prio Sync pulse intr
IRQ
Real Time Interrupt
Enhanced Capture Timer channel 0
Enhanced Capture Timer channel 1
Enhanced Capture Timer channel 2
Enhanced Capture Timer channel 3
Enhanced Capture Timer channel 4
Enhanced Capture Timer channel 5
Enhanced Capture Timer channel 6
Enhanced Capture Timer channel 7
Enhanced Capture Timer overflow
Pulse accumulator A overflow
Pulse accumulator input edge
SPI0
COPCTL (CME, FCME)
COP rate select
None
None
None / BFRIER (XSYNIE)
INTCR (IRQEN)
CRGINT (RTIE)
TIE (C0I)
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
TSCR2 (TOF)
PACTL (PAOVI)
PACTL (PAI)
SP0CR1 (SPIE, SPTIE)
SC0CR2
(TIE, TCIE, RIE, ILIE)
SC1CR2
(TIE, TCIE, RIE, ILIE)
ATD0CTL2 (ASCIE)
ATD1CTL2 (ASCIE)
PTJIF (PTJIE)
PTHIF (PTHIE)
MCCTL (MCZI)
$FFD6, $FFD7
SCI0
I-Bit
$D6
$FFD4, $FFD5
SCI1
I-Bit
$D4
$FFD2, $FFD3
$FFD0, $FFD1
$FFCE, $FFCF
$FFCC, $FFCD
$FFCA, $FFCB
ATD0
ATD1
Port J
Port H
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
$D2
$D0
$CE
$CC
$CA
Modulus Down Counter underflow