- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371790 > HD49335F (Renesas Technology Corp.) CDS/PGA AND 10-bit A/D TG Converter PDF資料下載
參數(shù)資料
| 型號： | HD49335F |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | CDS/PGA AND 10-bit A/D TG Converter |
| 中文描述： | 的CDS / PGA和10位A / D轉(zhuǎn)換器熱 |
| 文件頁數(shù)： | 11/30頁 |
| 文件大?。?/td> | 323K |
| 代理商： | HD49335F |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當(dāng)前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
HD49335F/HF
Rev.1.0, Feb.25.2004, page 11 of 29
Detailed Timing Specifications
Detailed Timing Specifications when CDSIN Input Mode is Used
Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing
specification.
CDS_in
SP1
Vth
(2)
(3)
SP2
ADCLK
(7)
Vth
Vth
(8)
(9)
(10)
(4)
(1)
(5)
(11)
(6)
(13)
(12)
D0 to D9
H1
Black
level
Signal
level
Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used
Table 8
Timing Specifications when the CDSIN Input Mode is Used
No.
(1)
(2)
(3)
(4)
(5)
(6)
(7), (8) ADCLK t
WH
min./t
WL
min
(9)
ADCLK rising to digital output
holding time
(10)
ADCLK rising to digital output delay time
(11)
H1 rising to ADCLK rising time
(12)
H1 rising to SPSIG falling time
(13)
H1 rising to SPBLK falling time
Timing
Black-level signal fetch time
SP1 ‘Hi’ period
Signal-level fetch time
SP2 ‘Hi’ period
SP1 falling to SP2 falling time
SP1 falling to ADCLK rising inhibit time
Symbol
t
CDS1
t
CDS2
t
CDS3
t
CDS4
t
CDS5
t
CDS6
t
CDS7, 8
t
CHLD9
t
COD10
t
CDS11
t
CDS12
t
CDS13
Min
—
Typ
×
0.8
—
Typ
×
0.8
Typ
×
0.85
—
11
—
—
—
—
—
Typ
(1.5)
1/4f
CLK
(1.5)
1/4f
CLK
1/2f
CLK
(5)
—
(7)
(16)
(1/4f
CLK
)
(1/f
CLK
)
(1/2f
CLK
)
Max
—
Typ
×
1.2
—
Typ
×
1.2
Typ
×
1.15
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OBP Detailed Timing Specifications
Figure 4 shows the OBP detailed timing specifications.
The OB period is from the fifth to the twelfth clock cycle after the OB pulse is inputted. The average of the black
signal level is taken for eight input cycles during the OB period and it becomes the clamp level (DC standard).
CDS_in
OBP
N
N+1
N+5
N+12
N+13
Note:
OB pulse > 2 clock cycles
OB period *
1
1. Shifts
±
1 clock cycle depending on the OBP input timing.
Figure 4 OBP Detailed Timing Specifications
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD49335HF | CDS/PGA AND 10-bit A/D TG Converter |
| HD49338F | CDS/PGA & 12-bit A/D Converter |
| HD49338HF | CDS/PGA & 12-bit A/D Converter |
| HD49351BP | CDS/PGA & 10-bit A/D TG Converter |
| HD49351HBP | CDS/PGA & 10-bit A/D TG Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD49335HF | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA AND 10-bit A/D TG Converter |
| HD49335HNP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 10-bit A/D TG Converter |
| HD49335NP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 10-bit A/D TG Converter |
| HD49338F | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 12-bit A/D Converter |
| HD49338HF | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 12-bit A/D Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。