
HD49335F/HF
Rev.1.0, Feb.25.2004, page 14 of 29
Absolute Maximum Ratings
(Ta = 25
°
C)
Item
Power supply voltage
Analog input voltage
Digital input voltage
Operating temperature range
Power dissipation
Storage temperature
Power supply voltage
Note: AV
DD
, AV
SS
are analog power
source systems
of CDS, PGA, and ADC.
DV
DD
1, DV
SS
1 are digital power source systems of CDS, PGA and ADC.
DV
DD
2, DV
SS
2 are buffer power source systems of ADC output.
DV
DD
3, DV
SS
3 are general digital power source systems of TG.
DV
DD
4, DV
SS
4 are buffer power source systems of H1 and H2.
Pin 2 multi bonds the DV
SS
1 and DV
SS
2
When pin 64 is set to Low, pin 41 = STROB output, pin 39 = SUB_SW output
When Hi, pin 41 = Vgate input, pin 39 = ADCK input
Electrical Characteristics
Symbol
V
DD
V
IN
V
I
Ta
Pt
Tstg
Vopr
Ratings
4.1
–0.3 to AV
DD
+0.3
–0.3 to DV
DD
+0.3
–20 to +85
590
–55 to +125
2.70 to 3.30
Unit
V
V
V
°C
mW
°C
V
(Unless othewide specified, Ta = 25°C, AV
DD
= 3.0 V, DV
DD
= 3.0 V, and R
BIAS
= 33 k
)
Items Common to CDSIN and ADCIN Input Modes
Item
Symbol
Min
Typ
Power supply voltage
range
f
CLK
hi
20
—
Conversion frequency
f
CLK
low
5.5
—
V
IH2
DV
DD
3.0
2.25
×
V
IL2
0
—
Max
3.30
Unit
V
Test Conditions
Remarks
V
DD
2.70
3.00
36
25
DV
DD
MHz
MHz
V
LoPwr = low *
2
LoPwr = high *
2
HD49335HF
HD49335F
CS, SCK, SDATA
—
Digital input voltage
DV
DD
3.0
0.6
×
V
V
OH
V
OL
I
IH
I
IL
RES
INL
DNL+
DNL–
I
SLP
DV
DD
–0.5
—
—
–50
10
—
—
–0.99
–100
—
—
—
—
10
(2)
0.3
–0.3
0
—
0.5
50
—
10
—
0.99
—
100
V
V
μ
A
μ
A
bit
LSBp-p
LSB
LSB
μ
A
I
OH
= –1 mA
I
OL
= +1 mA
V
IH
= 3.0 V
V
IL
= 0 V
f
CLK
= 25 MHz
f
CLK
= 25 MHz
f
CLK
= 25 MHz
Digital input pin is
set to 0 V, output
pin is open
Digital I/O pin is set
to 0 V
*1
*1
Digital output voltage
Digital input current
ADC resolution
ADC integral linearity
ADC differential linearity+
ADC differential linearity–
Sleep current
Standby current
I
STBY
—
3
5
mA
Notes: 1. Differential linearity is the calculated difference in linearity errors between adjacent codes.
2. 2 divided mode: f
CLK
= 1/2CLK_in
3 divided mode: f
CLK
= 1/3CLK_in
3. Values within parentheses ( ) are for reference.