參數(shù)資料
型號(hào)： HD49335F
廠商： Renesas Technology Corp.
英文描述： CDS/PGA AND 10-bit A/D TG Converter
中文描述： 的CDS / PGA和10位A / D轉(zhuǎn)換器熱
文件頁(yè)數(shù)： 19/30頁(yè)
文件大?。?/td> 323K
代理商： HD49335F
HD49335F/HF
Rev.1.0, Feb.25.2004, page 19 of 29
Output mode (D2 to D4 of address H’F1 and address H’F4 of D6)
It is a test mode. Combination details are table 3 to 5. Normally set to all 0.
SHA-fsel (D8 to D9 of address H’F1)
It is a LPF switching of SH amplifier. Frequency characteristics are referred to page 8. To get rough idea, set the
double cut off frequency point with using.
SHSW-fsel (D10 to D13 of address H’F1)
It is a time constant which sampling the black level of SH amplifier. Frequency characteristics are referred to page
8. To get rough idea, set the double cut off frequency point with using. S/N changes by this data, so find the
appropriate point with set data to up/down.
Test_I2 (D14 to D15 of address H’F1)
Current of ADC analog part can be set minutely. Normally use data = 0.
0: Default (100%)
1: 150%
2: 50%
3: 80%
Address
STD1[7:0] (L)
HGain-Nsel
STD2[15:8] (H)
1
1
1
1
0
0
1
0
D4
D3
D2
D1
D0 D15 D14 D13 D12 D11 D10 D9
D8
Clamp level
R
A
C
L
HGstop-Hsel
Clamp (D0 to D4 of address H’F2)
Determine the OB part level with digital code of ADC output.
Clamp level = setting data
×
2 + 14
Default data is 9 = 32 LSB.
HGstop-Hsel, HGain-Nsel (D8 to D11 of address H’F2)
Determine the lead-in speed of OB clamp. Details are referred to page 7. PGA gain need to be changed for switch
the high speed leading mode. Transfer the gain +1/–1 to previous field, its switch to high speed leading mode.
Low_PWR (D12 of address H’F2)
Switch circuit current and frequency characteristic.
Data = 0: 36 MHz guarantee
Data = 1: 25 MHz guarantee
ADSEL (D14 of address H’F2)
Data = 0: Select CDS_in
Data = 1: Select ADC_in
Reset (D15 of address H’F2)
Software reset.
Data = 1: Normal
Data = 0: Reset
Offset calibration should be done when starting up with using this bit. Details are referred to page 23.
Address
STD1[7:0] (L)
STD2[15:8] (H)
1
1
1
1
0
0
1
1
D4
D3
D2
D7
D6
D5
D1
D0 D15 D14 D13 D12 D11 D10 D9
D8
Address H'F3 are all testing data.
Normally set to all 0., or do not transfer the data.
相關(guān)PDF資料
PDF描述
HD49335HF CDS/PGA AND 10-bit A/D TG Converter
HD49338F CDS/PGA & 12-bit A/D Converter
HD49338HF CDS/PGA & 12-bit A/D Converter
HD49351BP CDS/PGA & 10-bit A/D TG Converter
HD49351HBP CDS/PGA & 10-bit A/D TG Converter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HD49335HF 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA AND 10-bit A/D TG Converter
HD49335HNP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 10-bit A/D TG Converter
HD49335NP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 10-bit A/D TG Converter
HD49338F 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 12-bit A/D Converter
HD49338HF 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:CDS/PGA & 12-bit A/D Converter
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