
HD49335F/HF
Rev.1.0, Feb.25.2004, page 15 of 29
Electrical Characteristics
(cont.)
(Unless othewide specified, Ta = 25°C, AV
DD
= 3.0 V, DV
DD
= 3.0 V, and R
BIAS
= 33 k
)
Items for CDSIN Input Mode
Item
Symbol
Min
Typ
Consumption current (1)
I
DD1
—
84
Max
96.6
Unit
mA
Test Conditions
f
CLK
= 36 MHz
Remarks
CDSIN mode
LoPwr = low
CDSIN mode
LoPwr = high
Refer to table 8
Consumption current (2)
I
DD2
—
58
66.7
mA
f
CLK
= 20 MHz
CCD offset tolerance range
Timing specifications (1)
Timing specifications (2)
Timing specifications (3)
Timing specifications (4)
Timing specifications (5)
Timing specifications (6)
Timing specifications (7)
Timing specifications (8)
Timing specifications (9)
Timing specifications (10)
Timing specifications (11)
Timing specifications (12)
Timing specifications (13)
Clamp level
V
CCD
t
CDS1
t
CDS2
t
CDS3
t
CDS4
t
CDS5
t
CDS6
t
CDS7
t
CDS8
t
CHLD9
t
COD10
t
CDS11
t
CDS12
t
CDS13
CLP(00)
CLP(09)
CLP(31)
AGC(0)
AGC(63)
AGC(127)
AGC(191)
AGC(255)
DLL_2
DLL_3
DLL_4
CLK_in3
(–100)
—
Typ
×
0.8
—
Typ
×
0.8
Typ
×
0.85
1
—
—
—
—
—
—
—
—
—
—
–4.4
4.1
12.5
21.0
29.4
11
7
5.5
28.6
—
(1.5)
1/4f
CLK
(1.5)
1/4f
CLK
1/2f
CLK
5
1/2f
CLK
1/2f
CLK
(7)
(16)
(1/4f
CLK
)
(1/f
CLK
)
(1/2f
CLK
)
(14)
(32)
(76)
–2.4
6.1
14.5
23.0
31.4
—
—
—
—
(100)
—
Typ
×
1.2
—
Typ
×
1.2
Typ
×
1.15
9
—
—
—
—
—
—
—
—
—
—
–0.4
8.1
16.5
25.0
33.4
25
11
7
28.6
mV
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LSB
LSB
LSB
dB
dB
dB
dB
dB
MHz
MHz
MHz
MHz
C
L
= 10 pF
C
L
= 10 pF
f
CLK
= 1/3CLK_in3
PGA gain at CDS input
*1
*2
*3
*4
DLL operation frequency
T/G 3/1divided operation
frequency range
H Buffer output voltage
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
2.94
—
2.89
—
2.91
—
2.85
—
2.69
—
2.81
—
2.97
22
2.94
50
2.96
36
2.93
60
2.86
115
2.90
78
—
47
—
112
—
78
—
129
—
262
—
141
V
MV
V
MV
V
MV
V
MV
V
mV
V
mV
30 mA Buff, I
OH
= –5 mA
30 mA Buff, I
OL
= +5 mA
14 mA Buff, I
OH
= –5 mA
14 mA Buff, I
OL
= +5 mA
10 mA Buff, I
OH
= –3 mA
10 mA Buff, I
OL
= +3 mA
4 mA Buff, I
OH
= –2 mA
4 mA Buff, I
OL
= +2 mA
2 mA Buff, I
OH
= –2 mA
2 mA Buff, I
OL
= +2 mA
I
OH
= –2 mA
I
OL
= +2 mA
RG output voltage
Notes: 1. Define digital output full scall with 1 V input as 0 dB.
2. Number of master steps: 60 steps, DLL current High
3. Number of master steps: 40 steps, DLL current Low
4. Number of master steps: 60 steps, DLL current Low
5. Values within parentheses ( ) are for reference.