參數(shù)資料
型號: HM5425801B
廠商: Hitachi,Ltd.
英文描述: 256M SSTL_2 interface DDR SDRAM(256M SSTL_2接口 DDR 同步DRAM)
中文描述: 256M DDR SDRAM的接口SSTL_2(256M SSTL_2接口的DDR同步DRAM)的
文件頁數(shù): 25/62頁
文件大?。?/td> 1016K
代理商: HM5425801B
HM5425161B, HM5425801B, HM5425401B Series
25
Write operation
: The burst length (BL) and the burst type (BT) of the mode register are referred when a
write command is issued. The burst length (BL) determines the length of a sequential data input by the write
command which can be set to 2, 4, or 8. The latency from write command to data input is fixed to 1. The
starting address of the burst read is defined by the column address (AY0 to AY8; the HM5425161B, AY0 to
AY9; the HM5425801B, AY0 to AY9, AY11; the HM5425401B), the bank select address (AX14, AX13)
which are loaded via the A0 to A14 pins in the cycle when the write command is issued. DQS, DQSU/DQSL
should be input as the strobe for the input-data and DM, DMU/DML as well during burst operation. t
WPREH
prior to the first rising edge of the DQS, the DQSU/DQSL should be set to Low and t
WPST
after the last falling
edge of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble.
The last low period of DQS is referred as wrtie postamble.
Write Operation
in1
in0
in1
in2
in3
in0
in1
in2
in3
in4
in5
in6
in7
CLK
CLK
Address
DQS*
Din
BL = 2
BL = 4
BL = 8
Command
BL: Burst length
t1
t0
t2
t3
t3.5
t4
t5
t6
t7
t8
t
RCD
t
WPST
DQS*:DQS,DQSU/DQSL
in0
ACTV
NOP
NOP
NOP
WRITE
t
WPREH
t
WPRES
#
!
"
#
Row
Column
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