參數(shù)資料
型號(hào)： HN29W25611T-50H
廠商： Hitachi,Ltd.
英文描述： 256M AND type Flash Memory More than 16,057-sector (271,299,072-bit)
中文描述： 256M超過(guò)16057型快閃記憶體部門（271299072位）
文件頁(yè)數(shù)： 24/42頁(yè)
文件大小： 331K
代理商： HN29W25611T-50H
HN29W25611T-50H
24
Serial Read (1) (2) Timing Waveform
CE
OE
WE
CDE
RES
t
CES
t
CWC
t
CWC
t
CEH
t
CPH
t
WPH
t
OER
t
WPH
t
WP
t
WP
t
WP
t
SAC
t
SAC
t
SAC
t
SP
t
OES
SC
t
WSD
t
SCC
t
SCC
t
SOH
I/O0 to I/O7
t
SCS
t
DS
t
RP
t
DBR
t
RBSY
t
RS
t
AS
t
AS
t
DH
t
DS
t
CDS
t
DF
t
SAC
t
CDH
t
WP
t
COH
t
DH
t
AH
t
AH
t
OEL
High-Z
RDY
/
Busy
D0out/D2048out
D1out/D2049out
D2111out/D2111out
00H
/F0H
SA(1)
Notes: 1. The status returns to the standby at the rising edge of
CE
.
2. Output data is not valid after the number of the SC pulse exceeds 2112 and 64 in the serial read mode (1)and (2), respectively.
3. After any commands are written, the status can return to the standby after the command FFH is input and
CE
turns to the V
IH
level.
t
OEWS
t
CDS
t
CDS
t
CDH
*
2
*
2
*
1
*
3
t
SPL
t
SH
t
SH
FFH
SA(2)
Serial Read (1) with CA before SC Timing Waveform
CE
OE
WE
CDE
RES
t
CES
t
CWC
t
WPH
t
CWC
t
CWC
t
CWC
t
CDS
t
CPH
t
CEH
t
WP
t
CDH
t
WPH
t
OER
t
WPH
t
WPH
t
WP
t
WP
t
WP
t
WP
t
WP
SC
t
SCD
t
WSD
t
SCC
t
SCC
t
SCC
t
SCC
t
OES
t
OES
t
WPH
t
CWC
t
OEWS
I/O0 to I/O7
t
SCS
t
DS
t
AS
t
AS
t
AS
t
AS
t
AH
t
AH
t
AS
t
SH
t
AS
t
AH
t
AH
t
OEL
t
AH
t
AH
t
SH
t
SH
t
SAC
t
SAC
t
SAC
t
SAC
t
DF
t
SP
t
RP
t
RBSY
t
DBR
t
RS
t
DH
t
OER
t
WP
t
SW
t
SP
t
SPL
t
WP
t
COH
h-1 cycle
High-Z
RDY
/
Busy
D(n)out
D(n+1)out
D(n+i)out
00H
SA(1)
CA(1)
CA(2)
CA(2)'
CA(1)'
D(m)out
D(m+1)out
D(m+j)out
FFH
Notes: 1. The status returns to the Standby at the rising edge of
CE
.
2. Output data is not valid after the number of the SC pulse exceeds (2112-n). (i
≤
2111-n, 0
≤
n
≤
2111)
3. Output data is not valid after the number of the SC pulse exceeds (2112-m). (j
≤
2111-m, 0
≤
m
≤
2111)
4. After any commands are written, the status can return to the standby after the command FFH is input and
CE
turns
to the V
level.
5. This interval can be repeated (h-1) cycle. (1
≤
h
≤
2048 + 64)
t
OEWS
t
CDS
t
CDS
t
CDH
*
2
*
2
*
3
*
3
*
1
*
5
*
4
t
SOH
t
SOH
t
SPL
t
OEL
t
SAC
t
SAC
t
SAC
t
DF
t
DS
t
DH
t
SAC
t
SH
SA(2)
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