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參數(shù)資料
| 型號： | HN29W25611T-50H |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 256M AND type Flash Memory More than 16,057-sector (271,299,072-bit) |
| 中文描述： | 256M超過16057型快閃記憶體部門（271299072位） |
| 文件頁數(shù)： | 25/42頁 |
| 文件大?。?/td> | 331K |
| 代理商： | HN29W25611T-50H |
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HN29W25611T-50H
25
Serial Read (1) with CA after SC Timing Waveform
CE
OE
WE
CDE
RES
t
CES
t
CWC
t
WPH
t
CWC
t
CDS
t
CPH
t
CEH
t
WP
t
CDH
t
WPH
t
OER
t
WP
t
CDH
t
WP
t
WP
SC
t
SCC
t
SCC
t
WSD
t
OES
t
SCC
t
SCC
t
OES
t
OEL
t
WPH
t
CWC
t
OEWS
I/O0 to I/O7
t
SCS
t
DS
t
AS
t
AS
t
SAC
t
SP
t
SH
t
AH
t
AH
t
SH
t
SH
t
SPL
t
SAC
t
SAC
t
SAC
t
DF
t
AH
t
AH
t
AS
t
AS
t
RP
t
DBR
t
RBSY
t
RS
t
DH
t
OER
t
WP
t
SW
t
SP
t
SAC
t
SPL
t
WP
t
COH
h cycle
High-Z
RDY
/
Busy
D0out
D1out
D(k)out
00H
SA(1)
CA(2)
CA(1)
D(m)out
D(m+1)out
D(m+j)out
FFH
Notes: 1. The status returns to the Standby at the rising edge of
CE
.
2. Output data is not valid after the number of the SC pulse exceeds 2112. (0
≤
k
≤
2111)
3. Output data is not valid after the number of the SC pulse exceeds (2112-m). (j
≤
2111-m, 0
≤
m
≤
2111)
4. After any commands are written, the status can return to the standby after the command FFH is input and
CE
turns to the V
IH
level.
5. This interval can be repeated h cycle. (1
≤
h
≤
2048 + 64)
t
OEWS
t
CDS
t
CDS
*
2
*
3
*
3
*
1
*
5
*
2
*
4
t
SOH
t
SOH
t
OEL
t
SAC
t
SAC
t
DF
t
DS
t
DH
t
SAC
t
SH
SA(2)
Erase and Status Data Polling Timing Waveform
(Sector Erase)
CE
OE
WE
CDE
RES
t
CES
t
CWC
t
CWC
t
CWC
t
CEH
t
OEPS
t
CE
t
COS
t
OE
t
RDY
t
ASE
t
WPH
t
WPH
t
WPH
t
WP
t
WP
t
WP
t
WP
t
CDH
t
SCHW
SC
I/O0 to I/O7
t
SCS
t
DS
t
DS
t
DB
t
RP
t
AS
t
AS
t
DH
t
DH
t
DF
t
DF
t
CDS
t
AH
t
AH
High-Z
High-Z
RDY
/
Busy
IO7 = V
OH
IO7 = V
OL
20H
SA(1)
SA(2)
Notes: 1. Any commands,including reset command FFH, cannot be input while RDY/
Busy
outputs a V
OL
.
2. The status returns to the standby status after RDY/
Busy
returns to High-Z.
t
OEWS
t
CDS
t
CDS
t
CDS
t
CDH
t
CDH
B0H
*
2
*
1
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