參數(shù)資料
型號(hào)： HN29W256H02TE
廠商： Hitachi,Ltd.
英文描述： Controller for AND Flash Memory(AND型閃速存儲(chǔ)器控制器)
中文描述： 控制器及快閃記憶體（及型閃速存儲(chǔ)器控制器）
文件頁數(shù)： 18/73頁
文件大小： 333K
代理商： HN29W256H02TE
HN29W256H02TE-1
2. Configuration and Status register (Address 202H)
This register is used for observing the card state.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CHGED
Note: initial value: 00H
SIGCHG
IOIS8
0
0
PWD
INTR
0
Name
R/W
Function
CHGED
(CARD->)
R
This bit indicates that CRDY/-BSY bit on Pin Replacement register is set to "1". When
CHGED bit is set to "1", -STSCHG pin is held "L" at the condition of SIGCHG bit set to
"1" and the card configured for the I/O interface.
SIGCHG
(HOST->)
R/W
This bit is set or reset by the host for enabling and disabling the status-change signal (-
STSCHG pin). When the card is configured I/O card interface and this bit is set to "1", -
STSCHG pin is controlled by CHGED bit. If this bit is set to "0", -STSCHG pin is kept
"H".
IOIS8
(HOST->)
R/W
The host sets this field to "1" when it can provide I/O cycles only with on 8 bit data bus
(D7 to D0).
PWD
(HOST->)
R/W
When this bit is set to "1", the card enters sleep state (Power Down mode). When this
bit is reset to "0", the card transfers to idle state (active mode). RRDY/-BSY bit on Pin
Replacement Register becomes BUSY when this bit is changed. RRDY/-BSY will not
become Ready until the power state requested has been entered. This card
automatically powers down when it is idle, and powers back up when it receives a
command.
INTR
(CARD->)
R
This bit indicates the internal state of the interrupt request. This bit state is available
whether I/O card interface has been configured or not. This signal remains true until
the condition which caused the interrupt request has been serviced. If interrupts are
disabled by the -IEN bit in the Device Control Register, this bit is a zero.
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參數(shù)描述
HN29W256H02TE-1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER
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