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參數(shù)資料
| 型號： | HN29W6411A |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64M AND type Flash Memory(64M AND型閃速存儲器) |
| 中文描述： | 6400 AND型快閃記憶體（64米及型閃速存儲器） |
| 文件頁數(shù)： | 10/30頁 |
| 文件大?。?/td> | 293K |
| 代理商： | HN29W6411A |
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HN29W6411A Series
10
Identifier Read
The manufacturer and device identifier code can be read in the identifier read mode. The manufacturer and
device identifier code is selected with
CDE
low and high, respectively.
Function Description
Status Register:
The HN29W6411A outputs the operation status data as follows: I/O7 pin outputs a
V
OL
to indicate that the memory is in either erase or program operation. The level of I/O7 pin turns to a
V
OH
when the operation finishes. I/O5 and I/O4 pins output V
OL
s to indicate that the erase and program
operations complete in a finite time, respectively. If these pins output V
OH
s, it indicates that these
operations have timed out. To execute other erase and program operation, the status data must be cleared
after a time out occurs. I/O3 pin outputs a V
OL
to indicate that the result of the erase verify is a "pass". If
the erase verify fails, I/O3 pin outputs a V
OH
. From I/O0 to I/O2 and I/O6 pins are reserved for future use.
The pins output V
OL
s and should be masked out during the status data read mode. The function of the
status register is summarized in the following table.
I/O
Flag definition
Ready/
Busy
Definition
I/O7
V
OH
= Ready, V
OL
= Busy
Outputs a V
OL
and should be masked out during the status data poling mode.
V
OH
= Fail, V
OL
= Pass
V
OH
= Fail, V
OL
= Pass
V
OH
= Fail (not erased), V
OL
= Pass (erased)
Outputs a V
OL
and should be masked out during the status data poling mode.
I/O6
Reserved
I/O5
Erase check
I/O4
Program check
I/O3
Erase verify
I/O2
Reserved
I/O1
Reserved
I/O0
Reserved
RDY/
Busy
:
The RDY/
Busy
signal also indicates the program/erase status of the flash memory. The
RDY/
Busy
signal is initially at a high impedance state. It turns to a V
OL
level after the fourth command for
either an erase or programming operation is input. After the erase or programming operation finishes, the
RDY/
Busy
signal turns back to the high impedance state.
WE
:
Commands and address are latched at the rising edge of
WE
.
SC:
Programming data is latched at the rising edge of SC.
CDE
:
Commands and data are latched when
CDE
is V
IL
and Address is latched when
CDE
is V
IH
.
RES
:
RES
pin must be kept at the V
ILR
(V
SS
±
0.2 V)
level when V
CC
is turned on and off. In this way, data
in the memory is protected against unintentional erase and programming.
RES
must be kept at the V
IHR
(V
CC
±
0.2 V) level during any operations such as programming, erase and read.
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相關(guān)代理商/技術(shù)參數(shù) |
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| HN29W6411ASERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AND Flash EEPROM |
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| HN29W6484AH03TE-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
| HN29W64AH05TE-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY CONTROLLER |
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