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參數(shù)資料
| 型號(hào)： | HSP43168JC-33Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 11/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIR FILTER DUAL 84-PLCC |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 濾波器類型： | FIR |
| 濾波器數(shù)： | 2 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC（29.21x29.21） |
| 包裝： | 管件 |
19
FN2808.12
July 27, 2009
Figure 25 shows the Timing Diagram required to obtained the
multiplexed/decimated output. The output of the two filters are
provided at by selecting the odd-decimation filter first, then the
even-decimation second using MUX0-1. Figure 26 shows the
Data Flow Diagram for the multiplexed decimation example.
h2(n)
FIRB
FIRA
FIGURE 24. DATA/COEFFICIENT ALIGNMENT FOR
MULTIPLEXED DECIMATION EXAMPLE
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D11
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
10
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
h1(n)
C11C10
C9 C8
C7 C6
C5 C4
C3 C2
C1 C0
23-TAPS
B(n)
24-TAPS
A(n)
01
2
3
520
21
22
0
01
2
0
CLK
INA0-9
CSEL0-4
TXFR
12
3
4
5
4
21
22
20
1
2
201
11
10
11
10
MUX0-1
ACCEN
FIGURE 25. TIMING DIAGRAM FOR MULTIPLEXED
DECIMATION EXAMPLE
FIGURE 26A. COMPUTATIONAL FLOW AS DATA SAMPLE 21 IS
CLOCKED INTO THE FEED-FORWARD STAGE
FIGURE 26B. COMPUTATIONAL FLOW AS DATA SAMPLE 22 IS
CLOCKED INTO THE FEED-FORWARD STAGE
+
ACCUMULATOR
D2
D5
D8
D11/2
1
2
34
5
6
18
19
20
15
16
17
12
13
14
21
7
8
911 10
12
CSEL = 0
(X3 + X21)D2 + (X6 + X18)D5 + (X9 + X15)D8 + (X12 + X12)D11/2
B DATA
FIR B
+
ACCUMULATOR
C2
C5
C8
C11
6
7
8
9
10
11
21
CSEL = 0
12
13
14
3
4
5
15
16
17
0
1
2
18
19
20
(X2 + X21)C2 + (X5 + X18)C5 + (X8 + X15)C8 + (X11 + X12)C11
FIR A
STREAM
A DATA
STREAM
+
ACCUMULATOR
D1
D4
D7
D10
6
1
29
4
5
12
7
8
19
20
21
16
17
18
13
14
15
10
11
22
13
CSEL = 1
(X2 + X22)D1 + (X5 + X19)D4 + (X8 + X16)D7 + (X11 + X13)D10
+ (X3 + X21)D2 + (X6 + X18)D5 + (X9 + X15)D8 + (X12 + X12)D11/2
FIR B
+
ACCUMULATOR
C1
C4
C7
C10
5
0
18
3
4
11
6
7
19
20
21
16
17
18
13
14
15
9
10
22
12
CSEL = 1
(X1 + X22)C1 + (X4 + X19)C4 + (X7 + X16)C7 + (X10 + X13)C10
+(X2 + X21)C2 + (X5 + X18)C5 + (X8 + X15)C8 + (X11 + X12)C11
FIR A
HSP43168
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP43168JC-40 | 制造商:Rochester Electronics LLC 功能描述:DUAL DIGITAL FILTER 84 PLCC, 40MHZ, COMM - Bulk |
| HSP43168JC-45 | 制造商:Rochester Electronics LLC 功能描述:DUAL DIGITAL FILTER 84 PLCC, 45MHZ, COMM - Bulk |
| HSP43168JC-45S5001 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP43168JI-40 | 制造商:Rochester Electronics LLC 功能描述:DUAL DIGITAL FILTER 84 PLCC 40MHZ,INDUSTRIAL TEMP - Bulk |
| HSP43168VC-33 | 制造商:Rochester Electronics LLC 功能描述:DUAL DIGITAL FILTER 100 PQFP, 33MHZ, COMM - Bulk 制造商:Harris Corporation 功能描述: 制造商:Intersil Corporation 功能描述: |
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