參數(shù)資料
型號: HSP43168JC-33Z
廠商: Intersil
文件頁數(shù): 6/25頁
文件大?。?/td> 0K
描述: IC FIR FILTER DUAL 84-PLCC
標準包裝: 15
濾波器類型: FIR
濾波器數(shù): 2
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 84-LCC(J 形引線)
供應商設備封裝: 84-PLCC(29.21x29.21)
包裝: 管件
14
FN2808.12
July 27, 2009
For this application, each filter cell is configured as an odd
length filter by writing 110H to the Control Register at
Address 000H. Even though an even tap filter is being
implemented, the filter cells must be configured as odd
length to ensure proper data flow. In addition, the filters
must be set to even symmetry. Also, the 4th bit at Control
Address 001H must be set to disable data reversal, and
TXFR must be tied low. Since an 8-tap asymmetric filter is
being implemented, two sets of coefficients must be stored.
These eight coefficients could be loaded into the first two
coefficient sets for FIR A by writing C0, C1, C2, C3, C7, C6,
C5, and C4 to address 100H, 101H, 102H, 103H, 108H,
109H, 10aH, and 10bH respectively.
The sum of products required for this 8-tap filter require
dynamic control over FWRD, RVRS, ACCEN, and
CSEL0-4. The relative timing of these signals is shown in
Figure 14.
FIGURE 13A. DATA SHIFTING DISABLED, BACKWARD
SHIFTING DECIMATION REGISTERS FEEDING
MULTIPLIERS
FIGURE 13B. SHIFTING OF DATA SAMPLE 7 INTO FIR CELL
ENABLED, FORWARD SHIFTING REGISTERS
FEEDING MULTIPLIERS
FIGURE 13C. DATA SHIFTING DISABLED, BACKWARD
SHIFTING DECIMATION REGISTERS FEEDING
MULTIPLIERS
FIGURE 13D. SHIFTING OF DATA SAMPLE 8 INTO FIR CELL
ENABLED, FORWARD SHIFTING REGISTERS
FEEDING MULTIPLIERS
FIGURE 13. DATA FLOW DIAGRAMS FOR 8-TAP ASYMMETRIC FILTER
6
5
4
0
1
2
3
C0
C1
C2
C3
(X0)C0 + (X1)C1 + (X2)C2 + (X3)C3
ACCUMULATOR
6
5
4
0
1
2
3
C7
C6
C5
C4
ACCUMULATOR
7
(X0)C0 + (X1)C1 + (X2)C2 + (X3)C3
+ (X7)C7 + (X6)C6 + (X5)C5 + (X4)C4
7
6
5
1
2
3
4
C0
C1
C2
C3
(X1)C0 + (X2)C1 +( X3)C2 + (X4)C3
ACCUMULATOR
76
5
12
3
4
C7
C6
C5
C4
8
(X1)C0 + (X2)C1 + (X3)C2 + (X4)C3
+ (X8)C7 + (X7)C6 + (X6)C5 + (X5)C4
HSP43168
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