參數(shù)資料
型號(hào)： HSP43168JC-33Z
廠商： Intersil
文件頁(yè)數(shù)： 3/25頁(yè)
文件大小： 0K
描述： IC FIR FILTER DUAL 84-PLCC
標(biāo)準(zhǔn)包裝： 15
濾波器類型： FIR
濾波器數(shù)： 2
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC（29.21x29.21）
包裝： 管件
11
FN2808.12
July 27, 2009
Two programmable Configuration Control Registers define a
unique FIR filter configuration. Register 000H has all filter
configuration unique parameters, while Register 001H, Bit 4, is
filter configuration unique. Table 7 details the configuration
control register values, the number of filter coefficient banks
required and the MUX1-0 control values for each filter example.
Example 1: Even-Tap Even Symmetric Filter
Example
The HSP43168 may be configured as two independent
8-tap symmetric filters as shown by the Block Diagram in
Figure 5. Each of the FIR cells takes advantage of
symmetric filter coefficients by pre-adding data samples
common to a given coefficient. As a result, each FIR cell
can implement an 8-tap symmetric filter using only four
multipliers. Similarly, when the HSP43168 is configured in
single filter mode a 16-tap symmetric filter is possible by
using the multipliers in both cells.
The operation of the FIR cell is better understood by comparing
the data and coefficient alignment for a given filter output,
Figure 6, with the data flow through the FIR cell, as shown in
Figure 7. The Block Diagrams in Figure 7 are a simplification of
the FIR cell shown in Figure 1. For simplicity, the ALUs and FIR
Cell Accumulators were replaced by adders, and the Pipeline
Delay Registers were omitted. In this example, we will only
show the data flow through one of the two FIR cells.
In Figure 7, the order of the data samples within the filter
cell is shown by the numbers in the forward and backward
shifting decimation paths. The output of the filter cell is
given by the equation at the bottom of each block diagram.
Figure 7A shows the data sample alignment at the pre-
adders for the data/coefficient alignment shown in Figure 6.
The dual filter application is configured by writing 1d0H to
address 000H via the microprocessor interface, CIN0-9, A0-8,
and WR. Since this application does not use decimation, the
4th bit of the Control Register at Address 001H must be set to
disable data reversal (see Table 2). Failure to disable data
reversal will produce erroneous results.
Using this architecture, only the unique coefficients need to
be stored in the Coefficient Bank. For example, the above
filter would be stored in the first coefficient set for FIR A by
writing C0, C1, C2, and C3 to Address 100H, 101H, 102H,
and 103H respectively. To write the same filter to the first
coefficient set for FIR B, the address sequence would
change to 104H, 105H, 106H, and 107H.
To operate the HSP43168 in this mode, TXFR is tied low to
ensure proper data flow; both FWRD and RVRS are tied low
to enable data samples from the forward and reverse data
paths to the ALUs for pre-adding; ACCEN is tied low to
prevent accumulation over multiple CLKs; SHFTEN is tied low
to allow shifting of data through the Decimation Registers;
MUX0-1 is programmed to multiplex the output the of either
FIR A or FIR B; CSEL0-4 is programmable to access the
stored coefficient set, in this example CSEL = 00000.
TABLE 7. CONFIGURATION CONTROL REGISTER VALUES
FILTER TYPE
REG
000
HEX
REG
001
HEX
# OF FILTER
COEFFICIENT
BANKS
MUX
1-0
Even Tap Even
Symmetric
1d0
010
1
10
Odd Tap Even Symmetric
110
010
1
10
Asymmetric
110
010
2
10
Even Tap Decimate by
N+1
1dN
000
N+1
10
Odd Tap Decimate by N+1
11N
000
N+1
10
Dual: Even and Odd Tap
Decimate by N+1
15N or
19N
000
Bit 4
N+1
10 and
11
HSP43168
INA0-9
INB0-9
OUT9-27
FIR A
FIR B
M
U
X
FIGURE 5. USING HSP43168 AS TWO INDEPENDENT FILTERS
8-TAP EVEN SYMMETRIC
AA
BB
FIGURE 7A. DATA FLOW AS DATA SAMPLE 7 IS CLOCKED
INTO THE FEED-FORWARD STAGE
C0
C1
C2
C3
C2
C1
C0
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
h(n)
x(n)
FIGURE 6. DATA/COEFFICIENT ALIGNMENT FOR 8-TAP
EVEN SYMMETRIC FILTER
8 TAPS
6
5
4
7
C0
C1
C2
C3
0
1
2
3
(X7 + X0)C0 + (X6 + X1)C1 + (X5 + X2)C2 + (X4 + X3)C3
+
HSP43168
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