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參數(shù)資料
| 型號： | HSP43168JC-33Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 9/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIR FILTER DUAL 84-PLCC |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 濾波器類型： | FIR |
| 濾波器數(shù)： | 2 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC（29.21x29.21） |
| 包裝： | 管件 |
17
FN2808.12
July 27, 2009
As in the 24-tap example, an output is required every third
CLK which allows 3 CLKs for computation. On each CLK,
one of three sets of coefficients are used to calculate the
filter taps. Since this is an odd length filter, the center
coefficient must be scaled by 1/2 to compensate for the
summation of the same data sample from the forward and
backward shifting decimation paths. The Block Diagrams in
Figure 20 show the data flow, and the accumulator output for
the data coefficient alignment is shown in Figure 21.
Proper data and coefficient alignment is achieved by asserting
TXFR once every three CLKs to switch the LIFOs which are
being read and written. In the odd-tap mode, TXFR is internally
delayed by one clock cycle with respect to ACCEN so that the
convolutional sum will be computed correctly. For odd length
filters, data prior to the last register in the forward decimation
path is routed to the feedback circuitry. As a result, TXFR
should be asserted one cycle prior to the input data samples
which align with the center tap. The timing relationship between
the CSEL0-5, ACCEN, and TXFR are shown in Figure 22.
FIGURE 20A. COMPUTATIONAL FLOW AS DATA SAMPLE 21 IS
CLOCKED INTO THE FEED-FORWARD STAGE
TXFR TAKES AFFECT ON THIS CLOCK CYCLE
FIGURE 20B. COMPUTATIONAL FLOW AS DATA SAMPLE 22 IS
CLOCKED INTO THE FEED-FORWARD STAGE
FIGURE 20C. COMPUTATIONAL FLOW AS DATA SAMPLE 23 IS
CLOCKED INTO THE FEED-FORWARD STAGE
FIGURE 20D. COMPUTATIONAL FLOW AS DATA SAMPLE 24 IS
CLOCKED INTO THE FEED-FORWARD STAGE
TXFR TAKES AFFECT ON THIS CLOCK CYCLE
FIGURE 20. DATA FLOW DIAGRAMS FOR 23-TAP DECIMATE BY 3 SYMMETRIC FILTER
+
ACCUMULATOR
C2
C5
C8
C11/2
1
2
34
5
6
18
19
20
15
16
17
12
13
14
21
(X3 + X21)C2 + (X6 + X18)C5 + (X9 + X15)C8 + (X12 + X12)C11/2
7
8
911 10
12
CSEL = 0
+
ACCUMULATOR
C1
C4
C7
C10
6
1
29
4
5
12
7
8
19
20
21
16
17
18
13
14
15
10
11
22
13
(X2 + X22)C1 + (X5 + X19)C4 + (X8 + X16)C7 + (X11 + X13)C10
+ (X3 + X21)C2 + (X6 + X18)C5 + (X9 + X15)C8 + (X12 + X12)C11/2
CSEL = 1
+
ACCUMULATOR
C0
C3
C6
C9
5
6
18
9
4
20
21
22
17
18
19
14
15
16
23
11
12
7
13 14
10
(X1 + X23)C0 + (X4 + X20)C3 + (X7 + X17)C6 + (X14 + X10)C9
+ (X2 + X22)C1 + (X5 + X19)C4 + (X8 + X16)C7 + (X11 + X13)C10
+ (X3 + X21)C2 + (X6 + X18)C5 + (X9 + X15)C8 + (X12 + X12)C11/2
ACCEN ASSERTED
AND ACTIVE
TXFR ASSERTED
CSEL = 2
+
ACCUMULATOR
C2
C5
C8
C11/2
4
5
67
8
9
21
22
23
18
19
20
15
16
17
24
10
11
12
14 13
(X6 + X24)C2 + (X9 + X21)C5 + (X12 + X18)C8 + (X15 + X15)C11/2
15
CSEL = 0
HSP43168
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP43168JC-40 | 制造商:Rochester Electronics LLC 功能描述:DUAL DIGITAL FILTER 84 PLCC, 40MHZ, COMM - Bulk |
| HSP43168JC-45 | 制造商:Rochester Electronics LLC 功能描述:DUAL DIGITAL FILTER 84 PLCC, 45MHZ, COMM - Bulk |
| HSP43168JC-45S5001 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP43168JI-40 | 制造商:Rochester Electronics LLC 功能描述:DUAL DIGITAL FILTER 84 PLCC 40MHZ,INDUSTRIAL TEMP - Bulk |
| HSP43168VC-33 | 制造商:Rochester Electronics LLC 功能描述:DUAL DIGITAL FILTER 100 PQFP, 33MHZ, COMM - Bulk 制造商:Harris Corporation 功能描述: 制造商:Intersil Corporation 功能描述: |
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