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參數(shù)資料
| 型號： | HSP43168JC-33Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 8/25頁 |
| 文件大小： | 0K |
| 描述： | IC FIR FILTER DUAL 84-PLCC |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 濾波器類型： | FIR |
| 濾波器數(shù)： | 2 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC（29.21x29.21） |
| 包裝： | 管件 |
16
FN2808.12
July 27, 2009
Example 5: Odd-Tap Decimating Symmetric Filter
This example highlights the use of the HSP43168 as two
independent, 23-tap, symmetric, decimate by 3 filters. In this
example, the operational differences in the control signals
and data reversal structure may be compared to the
previously discussed even-tap decimating filter. Figure 19
shows two FIR cells. The data flow in this example uses only
one of the FIR cells.
FIGURE 17A. COMPUTATIONAL FLOW AS DATA SAMPLE 21 IS
CLOCKED INTO THE FEED-FORWARD STAGE
FIGURE 17B. COMPUTATIONAL FLOW AS DATA SAMPLE 22 IS
CLOCKED INTO THE FEED-FORWARD STAGE
FIGURE 17C. COMPUTATIONAL FLOW AS DATA SAMPLE 23 IS
CLOCKED INTO THE FEED-FORWARD STAGE
FIGURE 17D. COMPUTATIONAL FLOW AS DATA SAMPLE 24 IS
CLOCKED INTO THE FEED-FORWARD STAGE
FIGURE 17. DATA FLOW DIAGRAMS FOR 24-TAP DECIMATED BY 3 FIR FILTER
+
ACCUMULATOR
C2
C5
C8
C11
6
7
8
9
10
11
21
(X2 + X21)C2 + (X5 + X18)C5 + (X8 + X15)C8 + (X11 + X12)C11
CSEL = 0
12
13
14
3
4
5
15
16
17
0
1
2
18
19
20
+
ACCUMULATOR
C1
C4
C7
C10
5
0
18
3
4
11
6
7
19
20
21
16
17
18
13
14
15
9
10
22
12
(X1 + X22)C1 + (X4 + X19)C4 + (X7 + X16)C7 + (X10 + X13)C10
+(X2 + X21)C2 + (X5 + X18)C5 + (X8 + X15)C8 + (X11 + X12)C11
CSEL = 1
+
ACCUMULATOR
C0
C3
C6
C9
4
5
0
7
8
3
20
21
22
17
18
19
14
15
16
23
10
11
6
12 13
9
(X0 + X23)C0 + (X3 + X20)C3 + (X6 + X17)C6 + (X9 + X14)C9
+ (X1 + X22)C1 + (X4 + X19)C4 + (X7 + X16)C7 + (X10 + X13)C10
+ (X2 + X21)C2 + (X5 + X18)C5 + (X8 + X15)C8 + (X11 + X12)C11
CSEL = 2
ACCEN ASSERTED
AND ACTIVE
TXFR ASSERTED
AND ACTIVE
+
ACCUMULATOR
C2
C5
C8
C11
3
4
56
7
8
21
22
23
18
19
20
15
16
17
24
9
10
11
13 12
(X5 + X24)C0 + (X8 + X21)C5 + (X11 + X18)C8 + (X14 + X15)C11
14
CSEL = 0
01
2
3
5
21
22
23
0
01
2
0
CLK
INA0-9
CSEL0-4
ACCEN
TXFR
12
3
4
5
4
22
23
21
1
2
012
Tied low.
FIGURE 18. CONTROL SIGNAL TIMING FOR 24-TAP
DECIMATE X3 FILTER
FWRD
RVRS
SHIFTEN
HSP43168
INA0-9
INB0-9
OUT9-27
FIR A
FIR B
M
U
X
FIGURE 19. USING HSP43168 AS TWO INDEPENDENT FILTERS
ODD-TAP DECIMATING
AA
BB
HSP43168
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP43168JC-40 | 制造商:Rochester Electronics LLC 功能描述:DUAL DIGITAL FILTER 84 PLCC, 40MHZ, COMM - Bulk |
| HSP43168JC-45 | 制造商:Rochester Electronics LLC 功能描述:DUAL DIGITAL FILTER 84 PLCC, 45MHZ, COMM - Bulk |
| HSP43168JC-45S5001 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP43168JI-40 | 制造商:Rochester Electronics LLC 功能描述:DUAL DIGITAL FILTER 84 PLCC 40MHZ,INDUSTRIAL TEMP - Bulk |
| HSP43168VC-33 | 制造商:Rochester Electronics LLC 功能描述:DUAL DIGITAL FILTER 100 PQFP, 33MHZ, COMM - Bulk 制造商:Harris Corporation 功能描述: 制造商:Intersil Corporation 功能描述: |
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