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參數(shù)資料
| 型號(hào)： | HY5PS121623LF |
| 英文描述： | 32Mx16|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| 中文描述： | 32Mx16 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內(nèi)存- 512M |
| 文件頁數(shù)： | 26/66頁 |
| 文件大?。?/td> | 862K |
| 代理商： | HY5PS121623LF |
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Rev. 0.52/Nov. 02 26
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
CAS LATENCY
The CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the
first burst of output data. The latency can be programmed 3, 4 or 5 clocks. If a Read command is registered at clock
edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. Reserved states
should not be used as unknown operation or incompatibility with future versions may result.
DLL RESET
A DLL reset is inititated by issuing a Mode Register Set command with bit A8 set to one during initialization sequence.
A DLL reset command must be issued to ensure proper device operation. It should be followed by a Mode Register Set
command. Fot the stablization of DLL and proper device operation, minimum 200 clock cycles are required between
DLL reset and any read command.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5PS12423F | 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12423LF | 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12823F | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12823LF | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5P | Current Transducers HY 5 to 25-P/SP1 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5PS12421AF | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12421AF-C3 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12421AF-C4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12421AF-E3 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12421AFP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
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