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參數(shù)資料
| 型號： | HY5PS121623LF |
| 英文描述： | 32Mx16|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| 中文描述： | 32Mx16 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內存- 512M |
| 文件頁數(shù)： | 42/66頁 |
| 文件大?。?/td> | 862K |
| 代理商： | HY5PS121623LF |
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Rev. 0.52/Nov. 02 42
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
Burst Write Opeation
Burst write command is issued by activating CS, CAS, WE and deactivating RAS at the rising edge of clock. Bank
address and column address provided on inputs BA0~BA1 and A0~A13 selects the bank and starting column address
for burst operation. Before the burst write command, the bank must be activated earlier. Write command to data-in
delay is determined by WL (Write latency). WL is RL-1, it’s equal to AL+CL-1.
A data strobe signal pair (DQS and /DQS) should be driven low (preamble) one clock prior to the WL. The first data bit
of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The sub-
sequent burst bit data are issued on successive edges of the DQS until the write burst is completed. The tDQSS speci-
fication must be satisfied for write cycles. To complete burst write operation, write recovery time (tWR) must be
maintained before precharge commaned issued.
DDR-II SDRAM do not allow any interruption of write burst due to the nature of 4bit prepatch architecture. Unlike
DDR-I SDRAM, write burst interupt by precharge, or another write command is prohibited during write burst. Burst
write command to the another bank can be given with having activated that bank where RAS to RAS delay (tRRD) is
satisfied.
/CK
CK
Active
Write
tRCD = 4clks
Write latency = 3clks
Active
Bank A
Write
Bank A
Write latency = 6clks
Additive Latency = 3clks
CMD
DQS
DQ
CMD
DQS
DQ
tRCD
PRE
Bank A
tWR
D0 D1 D2 D3
Write Burst Completion
D0 D1 D2 D3 D4 D5 D6 D7
CL=4CLKs, AL=0CLK, tWR=3CLKs, BL=4
CL=4CLKs, AL=3CLK, BL=8
相關PDF資料 |
PDF描述 |
|---|---|
| HY5PS12423F | 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12423LF | 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12823F | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12823LF | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5P | Current Transducers HY 5 to 25-P/SP1 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HY5PS12421AF | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12421AF-C3 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12421AF-C4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12421AF-E3 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
| HY5PS12421AFP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
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