參數(shù)資料
型號(hào)： HY5PS121623LF
英文描述： 32Mx16|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
中文描述： 32Mx16 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內(nèi)存- 512M
文件頁數(shù)： 32/66頁
文件大?。?/td> 862K
代理商： HY5PS121623LF
Rev. 0.52/Nov. 02 32
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
OCD impedance adjust(continued)
For proper operation of adjust mode, WL = RL - 1 = AL + CL -1 clocks and tDS/tDH should be met as the following tim-
ing diagram. For input data pattern for adjustment, DT0-DT3 is a fixed order and “not affected by MRS addressing
mode (ie. sequential or interleave)
Drive Mode
Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR-II SDRAM Driver impedance before
OCD impedance adjustment. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all
output drivers are turned off tOIT after “OCD calibration mode exit” command as the following timing diagram.
CMD
EMRS
NOP
NOP
NOP
NOP
NOP
EMRS
NOP
D
T0
D
T1
D
T2
D
T3
tWR
tDStDH
WL
CK
CK
DQS_in
DQ_in
OCD adjust mode
OCD calibration mode exit
CMD
tOIT(0~12ns)
CK
CK
DQS
DQS
DQ
tOIT(0~12ns)
Hi-Z
Hi-Z
DQS high & DQS low for Drive(1), DQS low & DQS high for Drive(0)
DQs high for Drive(1)
DQs low for Drive(0)
Enter Drive mode
OCD calibration mode exit
NOP
EMRS
NOP
NOP
NOP
EMRS
相關(guān)PDF資料
PDF描述
HY5PS12423F 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
HY5PS12423LF 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
HY5PS12823F 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
HY5PS12823LF 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
HY5P Current Transducers HY 5 to 25-P/SP1
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