參數(shù)資料
型號： HY5PS121623LF
英文描述： 32Mx16|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
中文描述： 32Mx16 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內(nèi)存- 512M
文件頁數(shù)： 52/66頁
文件大?。?/td> 862K
代理商： HY5PS121623LF
Rev. 0.52/Nov. 02 52
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
Write with Auto Precharge
If A10 is high when wrtie command is issued, DRAM perform write with auto precharge. When write with auto pre-
charge command is issued, internal Precharge start automatically. If tRAS minimum is satisfied, internal precharge
start at write recovery delay later after the completion of the burst write. If tRAS minimum is not satisfied, internal
precharge starting point is delayed until tRAS minimum is satisfied. The bank undergoing auto-precharge from the
completion of the write burst may be reactivated if the following two conditions are satisfied.
1. The data-in to bank activate delay time (tWR+tRP) has been satisfied.
2. The RAS cycle time (tRC) from the previous bank activation has been satisfied.
/CK
CK
tWR = 4clks
CMD
DQS
DQ
WBank A
Write latency= 4clks
D0 D1 D2 D3
Posted CAS AL=2
Write Burst Completion
ACT
Bank A
tRP = 4clks
CL=3CLKs, AL=2CLKs, BL=4, tWR=4CLKs, tRP=4CLKs (tWR+tRP Limit)
Auto Precharge Start
tRC min.
/CK
CK
tWR = 3clks
CMD
DQS
DQ
Write w/ AP
Bank A
Write latency= 4clks
D0 D1 D2 D3
Posted CAS AL=2
Write Burst Completion
BACT
tRP = 3clks
CL=3CLKs, AL=2CLKs, BL=4, tWR=3CLKs, tRP=4CLKs (tRC limit)
Auto Precharge Start
tRC min.
相關(guān)PDF資料
PDF描述
HY5PS12423F 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
HY5PS12423LF 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
HY5PS12823F 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
HY5PS12823LF 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
HY5P Current Transducers HY 5 to 25-P/SP1
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