參數(shù)資料
型號: HY5PS121623LF
英文描述: 32Mx16|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
中文描述: 32Mx16 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內(nèi)存- 512M
文件頁數(shù): 48/66頁
文件大?。?/td> 862K
代理商: HY5PS121623LF
Rev. 0.52/Nov. 02 48
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
Precharge Opeation
The precharge command is used to close or deactivate the open row in particular bank or the open row in all banks.
Precharge command is issued by activating CS, RAS, WE and deactivating CAS at the rising edge of clock. Bank
address and A10 provided on inputs BA0~BA1, A10 selects the bank to be precharged. Input A10 determines whether
one or all banks precharge. All bank precharged command is issued with A10=high, at that case, the other bank
address inputs are don’t care. But Bank address inputs select bank to be precharged, when precharge command is
issued with A10 = low. Once a bank has been precharged, it is in the idle state and must be activated prior to any read
or write commands being issued to that bank. The bank will be available for a subsequent row access some specified
time (tRP) after the precharge command is issued. Burst termination by precharge command is prohibited.
Bank Selection for Precharge
A10
BA0
BA1
Precharged Bank
Low
Low
Low
Bank 0 only
Low
Low
High
Bank 1 only
Low
High
Low
Bank 2 only
Low
High
High
Bank 3 only
High
Don’t care
Don’t care
All Banks 0~3
相關(guān)PDF資料
PDF描述
HY5PS12423F 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
HY5PS12423LF 128Mx4|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
HY5PS12823F 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
HY5PS12823LF 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
HY5P Current Transducers HY 5 to 25-P/SP1
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