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參數(shù)資料
| 型號(hào)： | HYB 39S16160CT-6 |
| 廠商： | SIEMENS AG |
| 英文描述： | 1M × 16-Mbit Synchronous DRAM for High-Speed Graphics Applications(16M位(1M × 16)同步動(dòng)態(tài)RAM(用于高速圖形場(chǎng)合)) |
| 中文描述： | 100萬× 16高兆同步DRAM高速圖形應(yīng)用程序（1,600位（1米× 16）同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器（用于高速圖形場(chǎng)合）） |
| 文件頁(yè)數(shù)： | 4/19頁(yè) |
| 文件大?。?/td> | 110K |
| 代理商： | HYB 39S16160CT-6 |
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HYB 39S16160CT-5.5/-6/-7
16-MBit Synchronous DRAM
Data Book
4
09.99
Signal Pin Description
Pin
Type
Signal Polarity Function
CLK
Input
Pulse
Positive
Edge
The System Clock Input. All of the SDRAM inputs are
sampled on the rising edge of the clock.
CKE
Input
Level
Active
High
Activates the CLK signal when high and deactivates the
CLK signal when low, thereby inititiates either the Power
Down mode, Suspend mode, or the Self Refresh mode.
CS
Input
Pulse
Active
Low
CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
RAS,
CAS,
WE
Input
Pulse
Active
Low
When sampled at the positive rising edge of the clock,
CAS, RAS, and WE define the command to be executed by
the SDRAM.
A0 - A10
Input
Level
–
During a Bank Activate command cycle, A0-A10 define the
row address (RA0 - RA10) when sampled at the rising
clock edge.
During a Read or Write command cycle, A0-A9 define the
column address (CA0 - CAn) when sampled at the rising
clock edge. CAn depends on the SDRAM organization.
1M
×
16 SDRAM CAn = CA7
In addition to the column address, A10 is used to invoke
autoprecharge operation at the end of the burst Read or
Write cycle. If A10 is high, autoprecharge is selected and
A11 defines the bank to be precharged (low = bank A,
high = bank B). If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 is used in
conjunction with A11 to control which bank(s) to precharge.
If A10 is high, both bank A and bank B will be precharged
regardless of the state of A11. If A10 is low, then A11 is
used to define which bank to precharge.
A11 (BS)
Input
Level
–
Selects which bank is to be active. A11 low selects bank A
and A11 high selects bank B.
DQx
Input
Output
Level
–
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
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| HYB 39S16160CT-7 | 1M × 16-Mbit Synchronous DRAM for High-Speed Graphics Applications(16M位(1M × 16)同步動(dòng)態(tài)RAM(用于高速圖形場(chǎng)合)) |
| HYB 39S256160T | 256-Mbit(4banks × 4MBit × 16) Synchronous DRAM(256M(4列 × 4M位 × 16)同步動(dòng)態(tài)RAM) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB39S16160CT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16 MBit Synchronous DRAM for High Speed Graphics Applications |
| HYB39S16160CT-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16 MBit Synchronous DRAM for High Speed Graphics Applications |
| HYB39S16160CT-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| HYB39S16320TQ-10 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Special Mode Registers Two color registers Burst Read with Single Write Operation |
| HYB39S16320TQ-5.5 | 制造商:Siemens 功能描述:Electronic Component |
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