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參數(shù)資料
| 型號： | HYB 39S16160CT-6 |
| 廠商： | SIEMENS AG |
| 英文描述： | 1M × 16-Mbit Synchronous DRAM for High-Speed Graphics Applications(16M位(1M × 16)同步動態(tài)RAM(用于高速圖形場合)) |
| 中文描述： | 100萬× 16高兆同步DRAM高速圖形應(yīng)用程序（1,600位（1米× 16）同步動態(tài)隨機存儲器（用于高速圖形場合）） |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 110K |
| 代理商： | HYB 39S16160CT-6 |
HYB 39S16160CT-5.5/-6/-7
16-MBit Synchronous DRAM
Data Book
9
09.99
Read and Write Access Mode
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the word line are fired. A CAS cycle is triggered by setting RAS high and
CAS low at a clock timing after a necessary delay,
t
RCD
, from the RAS timing. WE is used to define
either a Read (WE = H) or a Write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data Read or
Write operations are allowed at up to a 183 MHz data rate. The number of serial data bits is
determined by the burst length programmed at the mode set operation; that is, either 1, 2, 4, 8, or
full page (Note that full page is an optional feature in this device). Column addresses are segmented
by the burst length and serial data accesses are done within this boundary. The first column address
to be accessed is supplied at the CAS timing and the subsequent addresses are generated
automatically by the programmed burst length and its sequence. For example, in a burst length of
8 with interleave sequence, if the first address is ‘2’, then the rest of the burst sequence is 3, 0, 1,
6, 7, 4, and 5.
Full page burst operation is only possible using the sequential burst type and page length is a
function of the I/O organization and column addressing. Full page burst operation do not self
terminate once the burst length has been reached. In other words, unlike burst length of 2, 3, or 8,
full page burst continues until it is terminated using another command.
Similar to the page mode of conventional DRAM’s, burst Read or Write accesses on any column
address are possible once the RAS cycle latches sense amplifiers. The maximum refresh interval
time (
t
RAS
) limits the number of random column accesses. A new burst access can be done even
before the previous burst ends. The interrupt operation at every clock cycles is supported. When the
previous burst is interrupted, the remaining addresses are overwritten by the new address with the
full burst length. An interrupt which accompanies with an operation change from a Read to a Write
is possible by exploiting DQM to avoid bus contention.
When two banks are activated sequentially, interleaved bank Read or Write operations are
possible. Using the programmed burst length, alternate access and precharge operations on two
banks can implement fast serial data access modes among many different pages. After two banks
are activated, column to column interleave operation can be done between two different pages.
Refresh Mode
SDRAM has two refresh modes: CAS before RAS (CBR) Automatic Refresh and a Self Refresh. All
of banks must be precharged before applying any refresh mode. An on-chip address counter
increments the word and the bank addresses and no bank information is required for both refresh
modes. The chip enters the Automatic Refresh mode, when RAS and CAS are held low and CKE
and WE are held high at a clock timing. The mode restores word line after the refresh and no
external precharge command is necessary. A minimum
t
RC
time is required between two automatic
refreshes in a Burst Refresh mode. The same rule applies to any access command after the
Automatic Refresh operation.
The chip has an on-chip timer and the self Refresh Mode is available. It enters the mode when RAS,
CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the
clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation.
After the exit command, at least one
t
RC
delay is required prior to any access command.
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| HYB 39S256160T | 256-Mbit(4banks × 4MBit × 16) Synchronous DRAM(256M(4列 × 4M位 × 16)同步動態(tài)RAM) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB39S16160CT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16 MBit Synchronous DRAM for High Speed Graphics Applications |
| HYB39S16160CT-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16 MBit Synchronous DRAM for High Speed Graphics Applications |
| HYB39S16160CT-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| HYB39S16320TQ-10 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Special Mode Registers Two color registers Burst Read with Single Write Operation |
| HYB39S16320TQ-5.5 | 制造商:Siemens 功能描述:Electronic Component |
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