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參數(shù)資料
| 型號： | HYB 514100BJ-50 |
| 廠商： | SIEMENS AG |
| 英文描述： | 4M × 1-Bit Dynamic RAM(4M × 1位動(dòng)態(tài)RAM) |
| 中文描述： | 4米× 1位動(dòng)態(tài)隨機(jī)存儲(chǔ)器（4米× 1位動(dòng)態(tài)內(nèi)存） |
| 文件頁數(shù)： | 20/21頁 |
| 文件大小： | 108K |
| 代理商： | HYB 514100BJ-50 |
HYB 514100BJ-50/-60
4M
×
1 DRAM
Semiconductor Group
20
1998-10-01
Test Mode Entry
Test Mode
The HYB 514100BJ is organized 4 194 304 words by 1-bit but can internally be configured as
524 288 words by 8-bits. A WE, CAS-before-RAS cycle puts the device into Test Mode.
In Test Mode, data is written into 8 sectors in parallel and retrieved the same way. If, upon reading,
all bits are equal, the data output pin indicates a “1”. If any of the bits differ, the data output pin
indicates a “0”. In Test Mode the 4M DRAM can be tested as if it were a 512K DRAM. Test Mode
is exited by any refresh operation which is not a WE, CAS-before-RAS cycle. Addresses A10R,
A10C and A0C do not care during Test Mode.
SPT03024
"H" or "L"
A0 A10
-
OH
OL
IH
IL
IL
DO
(Output)
V
WE
V
V
V
V
OFF
t
WTS
t
WTH
t
IH
IH
IL
IL
IH
CAS
V
V
V
RAS
V
V
RP
RPG
t
t
CP
t
CSR
t
CHR
t
Row
Address
Z
Hi
CRP
t
RAS
RC
t
RPC
t
ASR
t
t
t
RP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB514100BJ-50- | 4M x 1-Bit Dynamic RAM |
| HYB514100BJ-60 | 4M x 1-Bit Dynamic RAM |
| HYB 514171BJ-50 | 256k × 16-Bit Dynamic RAM(256k × 16位 動(dòng)態(tài) RAM) |
| HYB514171BJ-50 | 256k x 16-Bit Dynamic RAM |
| HYB514171BJ-50- | 256k x 16-Bit Dynamic RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB514100BJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 1-Bit Dynamic RAM |
| HYB514100BJ-50- | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 1-Bit Dynamic RAM |
| HYB514100BJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 1-Bit Dynamic RAM |
| HYB514100BJ-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
| HYB514100BJL-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
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