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參數(shù)資料
| 型號： | HYB 514100BJ-50 |
| 廠商： | SIEMENS AG |
| 英文描述： | 4M × 1-Bit Dynamic RAM(4M × 1位動態(tài)RAM) |
| 中文描述： | 4米× 1位動態(tài)隨機存儲器（4米× 1位動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 108K |
| 代理商： | HYB 514100BJ-50 |
HYB 514100BJ-50/-60
4M
×
1 DRAM
Semiconductor Group
8
1998-10-01
Notes
1. All voltages are referenced to
V
SS
2.
I
CC1
,
I
CC3
,
I
CC4
and
I
CC6
depend on cycle rate.
3.
I
CC1
and
I
CC4
depend on output loading. Specified values are measured with the output open.
4. Address can be changed once or less while RAS =
V
IL
. In the case of
I
CC4
it can be changed once
or less during a fast page mode cycle (
t
PC
).
5. An initial pause of 200
μ
s is required after power-up followed by 8 RAS cycles of which at least
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS
cycles are required.
6. AC measurements assume
t
T
= 5 ns.
7.
V
IH (MIN.)
and
V
IL (MAX.)
are reference levels for measuring timing of input signals. Transition times
are also measured between
V
IH
and
V
IL
.
8. Measured with a load equivalent to 2 TTL loads and 100 pF.
9. Operation within the
t
RCD (MAX.)
limit ensures that
t
RAC (MAX.)
can be met.
t
RCD (MAX.)
is specified as
a reference point only: If
t
RCD
is greater than the specified
t
RCD (MAX.)
limit, then access time is
controlled by
t
CAC
.
10.Operation within the
t
RAD (MAX.)
limit ensures that
t
RAC (MAX.)
can be met.
t
RAD (MAX.)
is specified as
a reference point only: If
t
RAD
is greater than the specified
t
RAD (MAX.)
limit, then access time is
controlled by
t
AA
.
11.Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
12.
t
OFF (MAX.)
defines the time at which the outputs achieve the open-circuit condition and are not
referenced to output voltage levels.
13.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only. If
t
WCS
>
t
WCS (MIN.)
, the cycle is an early write cycle
and the data out pin will remain open-circuit (high impedance) through the entire cycle; if
t
RWD
>
t
RWD (MIN.)
,
t
CWD
>
t
CWD (MIN.)
,
t
AWD
>
t
AWD(MIN.)
and
t
CPWD
>
t
CPWD (MIN.)
, the cycle is a read-
write cycle and DO will contain data read from the selected cells. If neither of the above sets of
conditions is satisfied, the condition of the DO pin (at access time) is indeterminate.
14.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
leading edge in read-write cycles.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB514100BJ-50- | 4M x 1-Bit Dynamic RAM |
| HYB514100BJ-60 | 4M x 1-Bit Dynamic RAM |
| HYB 514171BJ-50 | 256k × 16-Bit Dynamic RAM(256k × 16位 動態(tài) RAM) |
| HYB514171BJ-50 | 256k x 16-Bit Dynamic RAM |
| HYB514171BJ-50- | 256k x 16-Bit Dynamic RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB514100BJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 1-Bit Dynamic RAM |
| HYB514100BJ-50- | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 1-Bit Dynamic RAM |
| HYB514100BJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 1-Bit Dynamic RAM |
| HYB514100BJ-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
| HYB514100BJL-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
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