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參數(shù)資料
| 型號： | HYB18T1G160AF-3S |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 1 Gbit DDR2 SDRAM |
| 中文描述： | 1千兆位DDR2內存 |
| 文件頁數(shù)： | 61/89頁 |
| 文件大?。?/td> | 1261K |
| 代理商： | HYB18T1G160AF-3S |
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HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
INFINEON Technologies
Page 61 Rev. 1.02 May 2004
3. Truth Tables
3.1 Command Truth Table
Function
CKE
CS
RAS CAS
WE
BA0
BA1
BA2
A13-A11 A10
A9 - A0
Notes
Previous
Cycle
Current
Cycle
(Extended) Mode Register Set
H
H
L
L
L
L
BA
OP Code
1, 2
Auto-Refresh
H
H
L
L
L
H
X
X
X
X
1
Self-Refresh Entry
H
L
L
L
L
H
X
X
X
X
1
Self-Refresh Exit
L
H
H
X
X
X
X
X
X
X
1
Single Bank Precharge
H
H
L
L
H
L
BA
X
L
X
1,2
Precharge all Banks
H
H
L
L
H
L
X
X
H
X
1
Bank Activate
H
H
L
L
H
H
BA
Row Address
1, 2
Write
H
H
L
H
L
L
BA
Column
L
Column
1,2,3
Write with Auto-Precharge
H
H
L
H
L
L
BA
Column
H
Column
1,2,3
Read
H
H
L
H
L
H
BA
Column
L
Column
1,2,3
Read with Auto-Precharge
H
H
L
H
L
H
BA
Column
H
Column
1,2,3
No Operation
H
X
L
H
H
H
X
X
X
X
1
Device Deselect
H
X
H
X
X
X
X
X
X
X
1
Power Down Entry
H
L
H
X
X
X
X
X
X
X
1,4
L
H
H
H
Power Down Exit
L
H
H
X
X
X
X
X
X
X
1,4
L
H
H
H
1. All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
2. Bank addresses (BA0 ~ BA2) determine which bank is to be operated upon. For (E)MRS BAx selects an (Extended)
Mode Register.
3. Burst reads or writes at BL = 4 cannot be terminated. See sections “Reads interrupted by a Read” and “Writes inter-
rupted by a Write” in section 2.4.6 for details.
4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by
the refresh requirements outlined in section 2.7.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self
Refresh.
6. “X” means “H or L (but a defined logic level)”.
7. Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM
must be powered down and then restarted through the specified initialization sequence before normal operation can
continue.
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相關代理商/技術參數(shù) |
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| HYB18T1G400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 256M x 4, 68 Pin, Plastic, BGA |
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| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
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