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參數(shù)資料
| 型號： | HYB18T1G160AF-3S |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 1 Gbit DDR2 SDRAM |
| 中文描述： | 1千兆位DDR2內(nèi)存 |
| 文件頁數(shù)： | 82/89頁 |
| 文件大?。?/td> | 1261K |
| 代理商： | HYB18T1G160AF-3S |
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Page 82 Rev. 1.02 May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
8.3 Input and Data Setup and Hold Time
8.3.1 Timing Definition for Input Setup (tIS) and Hold Time (tIH)
Address and control input setup time (tIS) is referenced from the input signal crossing at the VIH(ac) level for a ris-
ing signal and VIL(ac) for a falling signal applied to the device under test. Address and control input hold time (tIH)
is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal
applied to the device under test..
8.3.2 Timing Definition for Data Setup (tDS) and Hold Time (tDH)
Data input setup time (tDS) with
differential data strobe
enabled MR[bit10]=0, is referenced from the input signal
crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal
crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under
test. DQS/DQS signals must be monotonic between VIL(dc)max and VIH(dc)min. Data input hold time (tDH) with
differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIL(dc) level to the
differential data strobe crosspoint for a rising signal and VIH(dc) to the differential data strobe crosspoint for a fall-
ing signal applied to the device under test. DQS/DQS signals must be monotonic between VIL(dc)max and
VIH(dc)min.
Data input setup time (tDS) with
single-ended data strobe
enabled MR[bit10]=1, is referenced from the input sig-
nal crossing at the VIH(ac) level to the data strobe crossing VREF for a rising signal, and from the input signal
crossing at the VIL(ac) level to the single-ended data strobe crossing VREF for a falling signal applied to the
device under test. Data input hold time (tDH) with single-ended data strobe enabled MR[bit10]=1, is referenced
from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing VREF for a rising signal
and VIH(dc) to the single-ended data strobe crossing VREF for a falling signal applied to the device under test.
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF
V
IL(dc)
max
V
IL(ac)
max
V
SS
tIS
tIH
tIS
tIH
CK
CK
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF
V
IL(dc)
max
V
IL(ac)
max
V
SS
tDStDH
tDS
V
REF
tDH
DQS
DQS
DQS
Differential Input
Waveform
Single-ended Input
Waveform
相關PDF資料 |
PDF描述 |
|---|---|
| HYB18T1G160AF-5 | 1 Gbit DDR2 SDRAM |
| HYB18T1G160AFL-5 | 1 Gbit DDR2 SDRAM |
| HYB18T1G400AF | 1 Gbit DDR2 SDRAM |
| HYB18T1G400AF-3 | 1 Gbit DDR2 SDRAM |
| HYB18T1G400AF-37 | 1 Gbit DDR2 SDRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T1G400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 256M x 4, 68 Pin, Plastic, BGA |
| HYB18T1G400AF-5 | 制造商:Infineon Technologies AG 功能描述:256M X 4 DDR DRAM, 0.6 ns, PBGA68 |
| HYB18T1G800BF-3S | 功能描述:IC DDR2 SDRAM 1GBIT 68TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應商設備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
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