參數(shù)資料
型號: HYB18T1G400AF-37
廠商: INFINEON TECHNOLOGIES AG
英文描述: 1 Gbit DDR2 SDRAM
中文描述: 1千兆位DDR2內(nèi)存
文件頁數(shù): 16/89頁
文件大小: 1261K
代理商: HYB18T1G400AF-37
Page 16 Rev. 1.02 May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
MRS Mode Register Operation Table (Address Input For Mode Set)
A8
DLL Reset
0
No
1
Yes
A12
Active Power-Down
Mode Select
0
Fast exit (use tXARD)
1
Slow exit (use tXARDS)
A11
A3
A4
A2
A1
Address Field
A10
A9
A8
A7
A6
A5
BT
Burst Length
Mode
Register
A6
A5
A4
Latency
Reserved
0
0
0
0
0
0
0
1
1
1
0
1
Reserved
2
(optional)
***)
3
1
1
0
0
0
1
4
5
1
1
1
1
0
1
Reserved
Reserved
Burst Type
0
Sequential
1
Interleave
BA1
BA0
TM CAS Latency
A7
Mode
0
Normal
1
Test
DLL
WR
0*
A11
A10
A9
WR **)
Reserved
2
0
0
0
0
0
1
0
0
1
1
1
0
0
1
0
3
4
5
1
1
1
0
1
1
1
0
1
6
Reserved
Reserved
A2
A1
A0
Burst Length
0
1
0
4
0
1
1
8
A13~
A15
A12
0*
0*
BA1
0
0
BA0
0
1
MRS mode
MRS
EMRS(1)
EMRS(2):
Reserved
EMRS(3):
Reserved
1
0
1
1
PD
BA2
0*
*) Must be programmed to 0 when setting the mode register. A13 ~ A15 and BA2 are reserved for future use
and must be programmed to 0 when setting the mode register MRS
**) The programmability of WR (Write Recovery) is for Writes with Auto-Precharge only and defines the time
when the device starts precharge internally. WR must be programmed to fulfill the minimum requirement for
the analogue tWR timing.
***) CAS Latency = 2 is implemented in this design, but functionality is not tested and guaranteed.
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HYB18T1G400AF-3S 1 Gbit DDR2 SDRAM
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