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參數(shù)資料
| 型號： | HYB18T1G400AF-37 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 1 Gbit DDR2 SDRAM |
| 中文描述： | 1千兆位DDR2內(nèi)存 |
| 文件頁數(shù)： | 67/89頁 |
| 文件大?。?/td> | 1261K |
| 代理商： | HYB18T1G400AF-37 |
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HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
INFINEON Technologies
Page 67 Rev. 1.02 May 2004
5.3 Output Buffer Levels
5.3.1 SSTL_18 Output DC Current Drive
5.3.3 OCD “Off-Chip Driver” Default Characteristics
Symbol
Parameter
SSTL_18 Class
II
Units
Notes
IOH
IOL
Output Minimum Source DC Current
-13.4
mA
1, 3, 4
Output Minimum Sink DC Current
13.4
mA
2, 3, 4
1. VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT-VDDQ) / IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ
- 280 mV.
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 ohm for values of VOUT between 0V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in note 1 and 2. They are used to test drive current capa-
bility to ensure VIHmin. plus a noise margin and VILmax. minus a noise margin are delivered to an SSTL_18 receiver. The
actual current values are derived by shifting the desired driver operating points along 21 ohm load line to define a convenient
current for measurement.
5.3.2 SSTL_18 Output AC Test Conditions
Symbol
Parameter
SSTL_18 Class
II
Units
Notes
VOH
VOL
VOTR
Minimum Required Output Pull-up
VTT + 0.603
VTT – 0.603
0.5 * VDDQ
V
1
Maximum Required Output Pull-down
V
1
Output Timing Measurement Reference Level
V
2
1. SSTL_18 test load for VOH and VOL is different from the reference load described in section 8.1 of this datasheet. The
SSTL_18 test load has a 20 Ohm series resistor additionally to the 25 Ohm termination resistor into VTT. The SSTL_18 definition
assumes that +/- 335 mV must be developed across the effectively 25 Ohm termination resistor (13.4 mA x 25 Ohm = 335 mV).
With an additional series resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to VTT, at the out-
put device (13.4 mA * 45 Ohm) = 603 mV).
2. The VDDQ of the device under test is referenced.
Symbol
Description
min.
nominal
max.
Unit
Notes
-
Output Impedance
12.6
18
23.4
Ohms
1,2
-
Pull-up / Pull down mismatch
0
-
4
Ohms
1, 2, 3
-
Output Impedance step size for OCD calibration
0
-
1.5
Ohms
8
Sout
Output Slew Rate
1.5
-
5.0
V / ns
1, 4, 5, 6,
7
1) VDDQ = 1.8 V
±
0.1 V; VDD = 1.8 V
±
0.1 V.
2) Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV;
(VOUT-VDDQ) / IOH must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ - 280 mV. Impedance measurement
condition for output sink dc current: VDDQ = 1.7 V; VOUT = -280 mV; VOUT / IOL must be less than 23.4 ohms for values of VOUT
between 0 V and 280 mV.
3) Mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and voltage.
4) Slew rates measured from VIL(ac) to VIH(ac) with the load specified in Section 8.2.
5) The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This
is verified by design and characterisation but not subject to production test.
6) DRAM output slew rate specification applies to 400, 533 and 667 MT/s speed bins.
7) Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and tQHS specifi-
cation.
8) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the
DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 +/- 0.75 ohms under nominal condi-
tions.
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| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
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