參數(shù)資料
型號(hào)： HYB18T1G400AF-37
廠商： INFINEON TECHNOLOGIES AG
英文描述： 1 Gbit DDR2 SDRAM
中文描述： 1千兆位DDR2內(nèi)存
文件頁數(shù)： 65/89頁
文件大?。?/td> 1261K
代理商： HYB18T1G400AF-37
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
INFINEON Technologies
Page 65 Rev. 1.02 May 2004
5.2 DC & AC Logic Input Levels
DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the
EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The
method by which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing
relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode,
these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinc-
tion in timing methods is verified by design and characterisatio but not subject to production test. In single ended
mode, the DQS (and RDQS) signals are internally disabled and don’t care.
5.2.1 Single-ended DC & AC Logic Input Levels
.
5.2.2 Single-ended AC Input Test Conditions
Symbol
Parameter
Min.
Max.
Units
VIH (dc)
DC input logic high
VREF + 0.125
VDDQ + 0.3
V
VIL (dc)
DC input low
- 0.3
VREF - 0.125
V
VIH (ac)
AC input logic high
VREF + 0.250
-
V
VIL (ac)
AC input low
-
VREF - 0.250
V
Symbol
Condition
Value
Units
Notes
VREF
Input reference voltage
0.5 * VDDQ
V
1, 2
VSWING(max) Input signal maximum peak to peak swing
1.0
V
1, 2
SLEW
Input signal minimum slew rate
1.0
V / ns
3, 4
1. This timing and slew rate definition is valid for all single-ended signals except tis, tih, tds, tdh.
2. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
3. The input signal minimum slew rate is to be maintained over the range from VIL(dc)max to VIH(ac)min for rising edges and
the range from VIH(dc)min to VIL(ac)max for falling edges as shown in the below figure.
4. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac)
to VIL(ac) on the negative transitions.
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF
V
IL(dc)
max
V
IL(ac)
max
V
SS
V
SWING(MAX)
delta TR
delta TF
Start of Falling Edge Input Timing
Start of Rising Edge Input Timing
V
IH(dc)
min - V
IL(ac)
max
delta TF
Falling Slew =
Rising Slew =V
IH(ac)
min - V
IL(dc)
max
delta TR
相關(guān)PDF資料
PDF描述
HYB18T1G400AF-3S 1 Gbit DDR2 SDRAM
HYB18T1G400AF-5 1 Gbit DDR2 SDRAM
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相關(guān)代理商/技術(shù)參數(shù)
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