- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370781 > HYB18T256160AF (INFINEON TECHNOLOGIES AG) 256 Mbi t DDR2 SDRAM PDF資料下載
參數(shù)資料
| 型號： | HYB18T256160AF |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256 Mbi t DDR2 SDRAM |
| 中文描述： | 256姆噸DDR2內(nèi)存 |
| 文件頁數(shù)： | 17/90頁 |
| 文件大小： | 1246K |
| 代理商： | HYB18T256160AF |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁
HYB18T256400/800/160AF
256Mb DDR2 SDRAM
INFINEON Technologies
Page 17 Rev. 1.02 May 2004
2.2.4 DDR2 SDRAM Extended Mode Register Set (EMRS(1))
The extended mode register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength,
additive latency, OCD program, ODT, DQS and output buffers disable, RQDS and RDQS enable. The default
value of the extended mode register EMRS(1) is not defined, therefore the extended mode register must be writ-
ten after power-up for proper operation. The extended mode register is written by asserting low on CS, RAS, CAS,
WE, BA1
and high on BA0, while controlling the state of the address pins. The DDR2 SDRAM should be in all
bank precharge with CKE already high prior to writing into the extended mode register. The mode register set
command cycle time (tMRD) must be satisfied to complete the write operation to the EMRS(1). Mode register con-
tents can be changed using the same command and clock cycle requirements during normal operation as long as
all banks are in precharge state.
EMRS(1) Extended Mode Register Operation Table (Address Input For Mode Set)
Address Field
RDQS
Extended Mode
Register
DLL
1
D.I.C
BA1 BA0
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Additive latency
A5
A4
A3 AdditiveLatency
0
0
0
0
0
1
0
1
0
0
1
2
0
1
1
1
0
0
1
0
1
3
4
Reserved
1
1
1
1
0
1
Reserved
Reserved
A9
0
0
A8
0
0
A7
0
1
OCD Calibration Program
OCD Cal. Mode Exit, maintain setting
Drive (1)
0
1
1
0
0
0
Drive (0)
Adjust mode
OCD program
0*
DQS
Rtt
A10
0
1
Enable
Disable
A0
0
DLL Enable
Enable
1
Disable
Rtt
A6
Rtt (nom.)
ODT disabled
75 ohm
0
1
A2
0
0
0
1
1
1
150 ohm
Reserved
DQS,(RDQS) Disable
A12
A13~A15
0*
Qoff
1
1
1
OCD Calibration default
*) must be programmed to 0 for compatibility with future DDR2 memory products.
A11
RDQS,(RQDS) Enable
0
Disable
1
Enable
A12
Qoff
0
1
Output buffers enabled
Output buffers disabled
BA2
0*
BA0
0
1
0
MRS mode
MRS
EMRS(1)
BA1
0
0
1
1
1
EMRS(2)
EMRS(3)
a)
b)
a) When Adjust mode is issued, AL from previously set value must be applied
b) After setting to default, OCD mode needs to be exited by setting A9~A7 to 000.
Refer to the following 2.2.2.5 section for detailed information.
a)
a) Disables DQ, DQS, DQS, RDQS, RDQS
A1
Output Driver
Impedence Control
Normal
W eak
Driver
Size
100%
60%
0
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB18T256160AF-3 | 256 Mbi t DDR2 SDRAM |
| HYB18T256160AF-37 | 256 Mbi t DDR2 SDRAM |
| HYB18T256160AF-5 | 256 Mbi t DDR2 SDRAM |
| HYB18T256160AL-3S | 256 Mbi t DDR2 SDRAM |
| HYB18T256400AF | 256 Mbi t DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
| HYB18T256800AF-5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
| HYB18T512400AF-5 | 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。