參數(shù)資料
型號(hào): HYB18T256160AF
廠商: INFINEON TECHNOLOGIES AG
英文描述: 256 Mbi t DDR2 SDRAM
中文描述: 256姆噸DDR2內(nèi)存
文件頁數(shù): 46/90頁
文件大小: 1246K
代理商: HYB18T256160AF
Page 46 Rev. 1.02 May 2004
INFINEON Technologies
HYB18T256400/800/160AF
256Mb DDR2 SDRAM
2.7.2 Burst Write followed by Precharge
Minimum Write to Precharge command spacing to the same bank =
WL + BL/2 + tWR
. For write cycles, a delay
must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued.
This delay is known as a write recovery time (t WR) referenced from the completion of the burst write to the Pre-
charge command. No Precharge command should be issued prior to the tWR delay, as DDR2 SDRAM does not
support any burst interrupt by a Precharge command. tWR is an analog timing parameter (see the AC table in this
datasheet) and is not the programmed value for tWR in the MRS.
Examples:
.
Burst Write followed by Precharge: WL = (RL - 1) = 3, BL = 4, tWR = 3
Burst Write followed by Precharge: WL = (RL - 1) = 4, BL = 4, tWR = 3
NOP
NOP
NOP
NOP
NOP
W RITE A
Post CAS
T0
T2
T1
T3
T4
T5
T6
T7
T8
WL = 3
BW-P3
CMD
DQ
NOP
DIN A0 DIN A1 DIN A2 DIN A3
tW R
Completion of
the Burst Write
Precharge
A
NOP
DQS,
DQS
CK, CK
NOP
NOP
NOP
NOP
NOP
W RITE A
Post CAS
T0
T2
T1
T3
T4
T5
T6
T7
T9
WL = 4
BW-P4
CMD
DQ
NOP
DIN A0 DIN A1 DIN A2 DIN A3
tW R
Completion of
the Burst Write
Precharge
A
NOP
DQS,
DQS
CK, CK
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