參數(shù)資料
型號(hào): HYB18T256160AF
廠(chǎng)商: INFINEON TECHNOLOGIES AG
英文描述: 256 Mbi t DDR2 SDRAM
中文描述: 256姆噸DDR2內(nèi)存
文件頁(yè)數(shù): 74/90頁(yè)
文件大?。?/td> 1246K
代理商: HYB18T256160AF
Page 74 Rev. 1.02 May 2004
INFINEON Technologies
HYB18T256400/800/160AF
256Mb DDR2 SDRAM
6.2 IDD Measurement Conditions (cont’d)
For testing the IDD parameters, the following timing parameters are used:
6.3 ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A6 & A2 in the EMRS(1) a “week” or “strong” termination can be selected. The current
consumption for any terminated input pin, depends on the input pin is in tri-state or driving “0” or “1”, as long a
ODT is enabled during a given period of time.
ODT current per terminated input pin:
Parameter
Symbol
-5
DDR2 -400
-3.7
DDR2 -533
-3S
DDR2 - 667
-3
DDR2 - 667
Unit
3-3-3
3
5
15
4-4-4
4
3.75
15
5-5-5
5
3
15
4-4-4
4
3
12
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh command
period
Active bank A to Active
bank B command delay
CL(IDD)
tCK(IDD)
tRCD(IDD)
tCK
ns
ns
tRC(IDD)
60
60
60
57
ns
1 kB page size
tRRD(IDD)
7.5
7.5
7.5
7.5
ns
Active to Precharge Command
tRASmin(IDD)
tRASmax(IDD)
tRP(IDD)
45
45
45
45
ns
ns
ns
70000
15
70000
15
70000
15
70000
12
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh com-
mand period
tRFC(IDD)
75
75
75
75
ns
EMRS(1) State
min.
typ.
max.
Unit
Enabled ODT current per DQ
added IDDQ current for ODT enabled;
ODT is HIGH; Data Bus inputs are FLOATING
IODTO
A6 = 0, A2 = 1
tbd.
tbd.
7.5
mA/DQ
A6 = 1, A2 = 0
tbd.
tbd.
3.75
mA/DQ
Active ODT current per DQ
added IDDQ current for ODT enabled;
ODT is HIGH; worst case of Data Bus inputs
are STABLE or SWITCHING.
IODTT
A6 = 0, A2 = 1
tbd.
tbd.
15
mA/DQ
A6 = 1, A2 = 0
tbd.
tbd.
7.5
mA/DQ
note: For power consumption calculations the ODT duty cycle has to be taken into account
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