參數(shù)資料
型號(hào): ICS1892Y-14
英文描述: 10Base-T/100Base-TX Integrated PHYceiver
文件頁數(shù): 113/148頁
文件大?。?/td> 816K
代理商: ICS1892Y-14
Chapter 9
Pin Diagram, Listings, and Descriptions
ICS1892, Rev. D, 2/26/01
February 26, 2001
113
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
9.2.4.2
MAC/Repeater Interface Pins for 100M Symbol Interface
Table 9-7
lists the MAC/Repeater Interface pin descriptions for the 100M Symbol Interface.
Table 9-7.
MAC/Repeater Interface Pins: 100M Symbol Interface
MII Pin
Name
100M
Symbol
Pin
Name
Pin
No.
Pin
Type
Pin Description
COL
49
No
Connect
Collision (Detect).
For the 100M Symbol Interface, this pin is a no connect. For
more information, see
Table 6-1
.
CRS
SCRS
50
Output
Symbol Carrier Sense.
This pin’s description is the same as that given in
Table 9-6
.
MDC
MDC
31
Input
Management Data Clock.
This pin’s description is the same as that given in
Table 9-6
.
MDIO
MDIO
30
Input/
Output
Management Data Input/Output.
This pin’s description is the same as that given in
Table 9-6
.
RXCLK
SRCLK
37
Symbol Receive Clock.
The ICS1892 sources the SRCLK to the MAC/repeater. The
ICS1892 uses SRCLK to synchronize the signals on the
SRD0–4 pins. The following table contrasts the behavior on the
SRCLK pin when the mode for the ICS1892 is either 10Base-T
or 100Base-TX.
Note:
The signal on the SRCLK pin is conditioned by RXTRI,
that is, the Receive (Interface) Tri-State signal.
100Base-TX
The SRCLK frequency is 25
MHz.
The ICS1892 generates
SRCLK from the MDI data
stream while there is a valid link
(that is, either data or IDLEs).
In the absence of a link, the
ICS1892 uses the REFIN clock
to generate the SRCLK.
The ICS1892 switches
between clock sources during
the period between when
SCRS is being asserted and
RXDV is being asserted. While
the ICS1892 is bringing up a
link, a clock phase change of
up to 360 degrees can occur.
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