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參數(shù)資料
| 型號： | ICS1892Y-14 |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁數(shù)： | 31/148頁 |
| 文件大?。?/td> | 816K |
| 代理商： | ICS1892Y-14 |
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Chapter 6
Interface Overviews
ICS1892, Rev. D, 2/26/01
February 26, 2001
31
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
6.7.2
Clock Source: Crystal
Figure 6-1
shows the recommended configuration when a crystal is used to supply the ICS1892 clock
source. As shown, connect the two leads of the crystal between the ICS1892 pins REF_IN and REF_OUT.
To properly load the crystal, also add two capacitors (C1 and C2 of
Figure 6-1
): one connected between
REF_IN and ground (digital domain) and one connected between REF_OUT and ground (digital domain).
Note:
Because a crystal is a tuned RLC circuit, crystal loading has a significant impact on the clock
source accuracy.
As revealed by an impedance analysis of the recommended crystal configuration circuit, capacitors C1 and
C2 are in series. In addition, the circuit has stray capacitance, which
Figure 6-1
shows as CS3 and CS4.
This stray capacitance is the collective result of board layout and pad capacitance.
Stray capacitance CS3 is in parallel with C1, depicted cumulatively as CL1. Stray capacitance CS4 is in
parallel with C2, depicted cumulatively as CL2. Therefore, the total capacitive load as viewed by the crystal
is the series sum of the two capacitors CL1 and CL2. (To add capacitors in series, add their inverse.)
If the capacitors C1 and C2 have the same value (which is recommended), then CL1 = CL2. In this case,
each capacitance CL1 and CL2 equals twice the rated load capacitance of the crystal. For example, if
CS3 = CS4 = 5 pF, and the rated capacitive load of the crystal is 25 pF, then C1 = C2 = 45 pF.
(CL1 = CL2 = 50 pF. Therefore, CL1 in parallel with CL2 equals 25 pF.)
Crystal accuracy is affected by load capacitance. The following factors also affect the crystal accuracy and
must be considered when selecting a crystal for a design:
The crystal cut. The crystal must be cut for accuracy. In some cases, this cut can require using a fixture
that has equivalent capacitive loading characteristics as the final application.
The crystal temperature characteristics
The crystal aging characteristics
CL1 and CL2, that is, the specific capacitive loading that occurs as a result of the particular printed circuit
board that is used and the board layout
Figure 6-1.
Recommended Configuration for a Crystal Clock Source
ICS1892
REF_IN
REF_OUT
C1
CS3
CL1
C2
CS4
CL2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893Y-10 | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893 | 3.3-V 10Base-T/100Base-TX Integrated PHYceiver⑩ |
| ICS2002 | Wavedec Digital Audio Codec |
| ICS2002Y | Wavedec Digital Audio Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1893 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893_09 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver? |
| ICS1893AF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AFI | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AFILF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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