參數(shù)資料
型號： ICS1892Y-14
英文描述： 10Base-T/100Base-TX Integrated PHYceiver
文件頁數(shù)： 29/148頁
文件大?。?/td> 816K
代理商： ICS1892Y-14
Chapter 6
Interface Overviews
ICS1892, Rev. D, 2/26/01
February 26, 2001
29
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
6.4
Link Pulse Interface
The Link Pulse Interface allows an application to control each step in the auto-negotiation process except
for the actual generation and reception of 10Base-T link pulses (that is, Normal Link Pulses). The ICS1892
MAC/Repeater Interface can be configured as a Link Pulse Interface as determined by ICS1892
configuration functions.
The Link Pulse Interface is selected as follows:
The HW/SW pin must be set for the hardware setting (logic low).
The MII/SI input pin must be set for the Symbol/Serial Interface (logic high).
The 10/LP input pin must be set for Link Pulse mode (logic high).
The 10/100SEL input pin must be set for 100M operations (logic high).
Although the 10/100SEL pin must be set for 100M operations, a Normal Link Pulse has the same ISO/IEC
definition regardless of whether the 10/100SEL pin is set for 10M (10 MHz) or 100M (100 MHz.)
The Link Pulse Interface allows the MAC/repeater to control the transmission of Normal Link Pulses to the
remote link partner, thereby allowing the MAC/repeater to control the auto-negotiation processes.
The Link Pulse Interface consists of the following five signals: LTCLK, LPTX, LRCLK, LPRX, and SD.
(When the ICS1892 MAC/Repeater Interface is configured for Link Pulse operations, its default MII pins are
redefined. For more information, see
Section 9.2.4.4, “MAC/Repeater Interface Pins for Link Pulse
Interface”
.)
Table 6-3
lists the ICS1892 pin mappings for the ICS1892 Link Pulse Interface mode.
Table 6-3.
Pin Mappings for Link Pulse Interface Mode
Default
10M / 100M
MII Pin Names
MAC/Repeater Interface Pin Mappings, Configured for
Link Pulse Interface Mode
COL
No connect
CRS
No connect
LSTA
SD
MDC
MDC
MDIO
MDIO
RXCLK
LRCLK
RXD0, RXD1, RXD2, RXD3 No connect
RXDV
No connect
RXER
LPRX
TXCLK
LTCLK
TXD0, TXD1, TXD2, TXD3
No connect
TXEN
No connect
TXER
LPTX
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