參數(shù)資料
型號： ICS1892Y-14
英文描述： 10Base-T/100Base-TX Integrated PHYceiver
文件頁數(shù)： 4/148頁
文件大?。?/td> 816K
代理商： ICS1892Y-14
ICS1892, Rev. D, 2/26/01
February 26, 2001
4
Table of Contents
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
Table of Contents
Section
Chapter 8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
Title
Page
Management Register Set................................................................... 58
Introduction to Management Register Set ................................................. 59
Management Register Set Outline ............................................................ 59
Management Register Bit Access ............................................................. 60
Management Register Bit Default Values .................................................. 60
Management Register Bit Special Functions ............................................. 61
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
Register 0: Control Register ...................................................................... 62
Reset (bit 0.15) .......................................................................................... 62
Loopback Enable (bit 0.14) ........................................................................ 63
Data Rate Select (bit 0.13) ........................................................................ 63
Auto-Negotiation Enable (bit 0.12) ............................................................ 63
Low Power Mode (bit 0.11) ........................................................................ 64
Isolate (bit 0.10) ......................................................................................... 64
Restart Auto-Negotiation (bit 0.9) .............................................................. 64
Duplex Mode (bit 0.8) ................................................................................ 65
Collision Test (bit 0.7) ................................................................................ 65
IEEE Reserved Bits (bits 0.6:0) ................................................................. 65
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10
8.3.11
8.3.12
8.3.13
Register 1: Status Register ........................................................................ 66
100Base-T4 (bit 1.15) ................................................................................ 66
100Base-TX Full Duplex (bit 1.14) ............................................................ 67
100Base-TX Half Duplex (bit 1.13) ............................................................ 67
10Base-T Full Duplex (bit 1.12) ................................................................. 67
10Base-T Half Duplex (bit 1.11) ................................................................ 67
IEEE Reserved Bits (bits 1.10:7) ............................................................... 68
MF Preamble Suppression (bit 1.6) ........................................................... 68
Auto-Negotiation Complete (bit 1.5) .......................................................... 68
Remote Fault (bit 1.4) ................................................................................ 69
Auto-Negotiation Ability (bit 1.3) ................................................................ 69
Link Status (bit 1.2) .................................................................................... 69
Jabber Detect (bit 1.1) ............................................................................... 70
Extended Capability (bit 1.0) ..................................................................... 70
8.4
Register 2: PHY Identifier Register ............................................................ 71
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