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參數(shù)資料
| 型號： | ICSSSTUAF32868BHLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA176 |
| 封裝： | LEAD FREE, MO-205/MO-255/MO-246, LFBGA-176 |
| 文件頁數(shù)： | 10/22頁 |
| 文件大?。?/td> | 538K |
| 代理商： | ICSSSTUAF32868BHLFT |
ICSSSTUAF32868B
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
18
ICSSSTUAF32868B
7102/2
Test Circuits and Waveforms (VDD = 1.8V ± 0.1V)
Simulation Load Circuit
Voltage and Current Waveforms Inputs Active and Inactive
Times
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Setup and Hold Times
Production-Test Load Circuit
Voltage Waveforms - Propagation Delay Times
NOTES:
1. CL includes probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and
Io = 0mA
3. All input pulses are supplied by generators having the following
characteristics: PRR
≤10MHz, Zo = 50Ω, input slew rate = 1 V/ns
±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per
measurement.
5. VTT = VREF = VDD/2
6. VIH = VREF + 250mV (AC voltage levels) for differential inputs.
VIH = VDD for LVCMOS input.
7. VIL = VREF - 250mV (AC voltage levels) for differential inputs.
VIL = GND for LVCMOS input.
8. VID = 600mV.
9. tPLH and tPHL are the same as tPDM.
CL =30 pF
RL =1K
Ω
DUT
Out
RL= 100
Ω
CLK Inputs
TL =50
Ω
TL =350ps, 50
Ω
Test Point
CLK
VDD
RL =1K
Ω
Test Point
VDD
0V
VDD/2
LVCMOS
RESET
Input
IDD
VDD/2
tINACT
tACT
10%
90%
VICR
VID
VICR
Input
tW
VREF
VIH
VIL
VREF
Input
VICR
VID
tSU
tH
CLK
ZO =50
Ω
Test
Point
RL =50
Ω
DUT
Out
CLK Inputs
CLK
VDD/2
CLK
ZO =50
Ω
ZO =50
Ω
Test
Point
Test
Point
CLK
VICR
VID
tPLH
tPHL
Output
VOH
VOL
VICR
VTT
CLK
VOH
VOL
VIH
VIL
tRPHL
VDD/2
VTT
LVCMOS
RESET
Input
Output
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