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參數(shù)資料
| 型號(hào)： | ICSSSTUAF32868BHLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 鎖存器 |
| 英文描述： | 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA176 |
| 封裝： | LEAD FREE, MO-205/MO-255/MO-246, LFBGA-176 |
| 文件頁(yè)數(shù)： | 12/22頁(yè) |
| 文件大小： | 538K |
| 代理商： | ICSSSTUAF32868BHLFT |
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ICSSSTUAF32868B
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
2
ICSSSTUAF32868B
7102/2
Features
28-bit 1:2 registered buffer with parity check functionality
Supports SSTL_18 JEDEC specification on data inputs
and outputs
Supports LVCMOS switching levels on CSGEN and
RESET inputs
Low voltage operation: VDD = 1.7V to 1.9V
Available in 176-ball LFBGA package
Applications
DDR2 Memory Modules
Provides complete DDR DIMM solution with
ICS98ULPA877A or IDTCSPUA877A
Ideal for DDR2 400, 533, and 667
Block Diagram
Q1A
Q1B
A7
A8
D
R
CK
Q
D1
CE
A2
TO 21 OTHER CHANNELS
(D2-D5, D7, D9-D12, D17-D28)
QCS0B
K2
L7
QODT0A,
QODT1A
QODT0B,
QODT1B
N2, P2
M7, M8
QCKE0A,
QCKE1A
QCKE0B,
QCKE1B
F2, E2
H8, F8
D
R
CK
Q
2
D
R
CK
Q
D
R
CK
Q
2
QCS1A
QCS1B
L8
J2
D
R
CK
Q
RESET
CLK
DCKE0,
DCKE1
CLK
DODT0,
DODT1
DCS0
CSGEN
DCS1
VREF
M2
L1
M1
A5, AB5
D1, C1
N1, P1
K1
L2
J1
2
One of 22 Channels
2
QCS0A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICSSSTUAF32869A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32869AHLF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAH32865A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
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| ICSSSTUAH32868A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
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