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參數(shù)資料
| 型號(hào)： | ICSSSTUAF32868BHLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA176 |
| 封裝： | LEAD FREE, MO-205/MO-255/MO-246, LFBGA-176 |
| 文件頁(yè)數(shù)： | 5/22頁(yè) |
| 文件大?。?/td> | 538K |
| 代理商： | ICSSSTUAF32868BHLFT |
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ICSSSTUAF32868B
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
13
ICSSSTUAF32868B
7102/2
DC Electrical Characteristics Over Operating Range
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, VDDQ/VDD = 2.5V ± 0.2V.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
VOH
Output HIGH Voltage
IOH = -6mA, VDDQ = 1.7V
1.2
V
VOL
Output LOW Voltage
IOL = 6mA, VDDQ = 1.7V
0.5
V
IIL
All Inputs
VI = VDD or GND; VDD = 1.9V
-5
+5
μA
IDD
Static Standby
IO = 0, VDD = 1.9V, RESET = GND
200
μA
Static Operating
IO = 0, VDD = 1.9V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK = CLK = VIH(AC)
or VIL(AC)
10
mA
IO = 0, VDD = 1.9V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK = VIH(AC), CLK =
VIL(AC)
200
IDDD
Dynamic Operating
(clock only)
IO = 0, VDD = 1.8V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK and CLK
switching 50% duty cycle
500
μA/Clock
MHz
Dynamic Operating
(per each data input)
1:2 mode
IO = 0, VDD = 1.8V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK and CLK
switching 50% duty cycle. One data
input switching at half clock frequency,
50% duty cycle.
44
μA/Clock
MHz/
Data
CI
Data Inputs
VI = VREF ± 250mV
2
3.5
pF
CLK and CLK
VICR = 0.9V, VIPP = 600mV
2.5
4
RESET
VI = VDD or GND
5
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