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參數(shù)資料
| 型號： | IDT70V7599S200BCI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| 中文描述： | 高速與3.3V 3.3V的128K的× 36 SYNCHRONOU開戶銀行可切換雙端口靜態(tài)RAM或2.5V的接口 |
| 文件頁數(shù)： | 18/22頁 |
| 文件大?。?/td> | 489K |
| 代理商： | IDT70V7599S200BCI |
6.42
IDT70V7599S
High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)
(1,6)
t
CYC2
NOTES:
1.
CE
0
,
BE
n
, and R/
W
= V
IL
; CE
1
and
REPEAT
= V
IH
.
2.
CE
0
,
BE
n
= V
IL
; CE
1
= V
IH
.
3. The "Internal Address" is equal to the "External Address" when
ADS
= V
IL
and equals the counter output when
ADS
= V
IH
.
4. No dead cycle exists during
REPEAT
operation. A READ or WRITE cycle may be coincidental with the counter
REPEAT
cycle: Address loaded by last valid
ADS
load will be accessed. For more information on
REPEAT
function refer to Truth Table II.
5.
CNTEN
= V
IL
advances Internal Address from‘An to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address
FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0.
7. For Pipelined Mode user should add 1 cycle latency for outputs as per timng waveformof read cycle for pipelined operations.
ADDRESS
An
CLK
DATA
IN
Dn
Dn + 1
Dn + 1
Dn + 2
ADS
CNTEN
t
CH2
t
CL2
5626 drw 18
(3)
INTERNAL
An
(5)
An + 1
An + 2
An + 3
An + 4
Dn + 3
Dn + 4
t
SA
t
HA
t
SAD
t
HAD
COUWRITE
WRITE WITH COUNTER
ADDRESS
WRITE
WITH COUNTER
t
SD
t
HD
t
SCN
t
HCN
Timing Waveform of Counter Repeat for Flow Through Mode
(2,6,7)
t
CYC2
ADDRESS
An
CLK
DATA
IN
R/
W
REPEAT
5626 drw 19
INTERNAL
(3)
ADDRESS
ADS
CNTEN
WRITE TO
ADS
ADDRESS
An
ADVANCE
COUNTER
WRITE TO
An+1
ADVANCE
COUNTER
WRITE TO
An+2
HOLD
COUNTER
WRITE TO
An+2
READ LAST
ADS
ADDRESS
An
DATA
OUT
t
SA
t
HA
,
An
t
SAD
t
HAD
t
SW
t
HW
t
SCN
t
HCN
t
SRPT
t
HRPT
t
SD
t
HD
t
CD1
An+1
An+2
An+2
An
An+1
An+2
An+2
D
0
D
1
D
2
D
3
An
An+1
An+2
An+2
ADVANCE
COUNTER
READ
An+1
ADVANCE
COUNTER
READ
An+2
HOLD
COUNTER
READ
An+2
(4)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT70V7599S200BF | HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V7599S | HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V7599S133BC | HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| IDT70V7599S133BCI | High Conductance Low Leakage Diode; Package: DO-35; No of Pins: 2; Container: Bulk |
| IDT70V7599S133BF | High Conductance Low Leakage Diode |
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