參數(shù)資料
型號： IDT70V7599S200BCI
廠商： Integrated Device Technology, Inc.
英文描述： HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
中文描述： 高速與3.3V 3.3V的128K的× 36 SYNCHRONOU開戶銀行可切換雙端口靜態(tài)RAM或2.5V的接口
文件頁數(shù)： 6/22頁
文件大?。?/td> 489K
代理商： IDT70V7599S200BCI
6.42
IDT70V7599S
High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Truth Table IRead/Write and Enable Control
(1,2,3,4)
Byte 3
I/O
27-35
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS
,
CNTEN
,
REPEAT
are set as appropriate for address access. Refers to Truth Table II for details.
3.
OE
is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
OE
3
CLK
CE
0
CE
1
BE
3
BE
2
BE
1
BE
0
R/
W
Byte 2
I/O
18-26
Byte 1
I/O
9-17
Byte 0
I/O
0-8
MODE
X
↑
H
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Deselected–Power Down
X
↑
X
L
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Deselected–Power Down
X
↑
L
H
H
H
H
H
X
High-Z
High-Z
High-Z
High-Z
All Bytes Deselected
X
↑
L
H
H
H
H
L
L
High-Z
High-Z
High-Z
D
IN
Write to Byte 0 Only
X
↑
L
H
H
H
L
H
L
High-Z
High-Z
D
IN
High-Z
Write to Byte 1 Only
X
↑
L
H
H
L
H
H
L
High-Z
D
IN
High-Z
High-Z
Write to Byte 2 Only
X
↑
L
H
L
H
H
H
L
D
IN
High-Z
High-Z
High-Z
Write to Byte 3 Only
X
↑
L
H
H
H
L
L
L
High-Z
High-Z
D
IN
D
IN
Write to Lower 2 Bytes Only
X
↑
L
H
L
L
H
H
L
D
IN
D
IN
High-Z
High-Z
Write to Upper 2 bytes Only
X
↑
L
H
L
L
L
L
L
D
IN
D
IN
D
IN
D
IN
Write to All Bytes
L
↑
L
H
H
H
H
L
H
High-Z
High-Z
High-Z
D
OUT
Read Byte 0 Only
L
↑
L
H
H
H
L
H
H
High-Z
High-Z
D
OUT
High-Z
Read Byte 1 Only
L
↑
L
H
H
L
H
H
H
High-Z
D
OUT
High-Z
High-Z
Read Byte 2 Only
L
↑
L
H
L
H
H
H
H
D
OUT
High-Z
High-Z
High-Z
Read Byte 3 Only
L
↑
L
H
H
H
L
L
H
High-Z
High-Z
D
OUT
D
OUT
Read Lower 2 Bytes Only
L
↑
L
H
L
L
H
H
H
D
OUT
D
OUT
High-Z
High-Z
Read Upper 2 Bytes Only
L
↑
L
H
L
L
L
L
H
D
OUT
D
OUT
D
OUT
D
OUT
Read All Bytes
H
X
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Outputs Disabled
5626 tbl 02
Truth Table IIAddress and Address Counter Control
(1,2,7)
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/
W
,
CE
0
, CE
1
,
BE
n and
OE
.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4.
ADS
and
REPEAT
are independent of all other memory control signals including
CE
0
, CE
1
and
BE
n
5. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other memory control signals including
CE
0
, CE
1
,
BE
n.
6. When
REPEAT
is asserted, the counter will reset to the last valid address loaded via
ADS
. This value is not set at power-up: a known location should be loaded
via
ADS
during initialization if desired. Any subsequent
ADS
access during operations will update the
REPEAT
address location.
7. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address
FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer
to Timng Waveformof Counter Repeat, page 18. Care should be taken during operation to avoid having both counters point to the same bank (i.e., ensure BA
0L
- BA
5L
≠
BA
0R
- BA
5R
), as this condition will invalidate the access for both ports. Please refer to the functional description on page 19 for details.
Address
Previous
Address
Addr
Used
CLK
ADS
CNTEN
REPEAT
(6)
I/O
(3)
MODE
An
X
An
↑
L
(4)
X
H
D
I/O
(n)
External Address Used
X
An
An + 1
↑
H
L
(5)
H
D
I/O
(n+1)
Counter Enabled—Internal Address generation
X
An + 1
An + 1
↑
H
H
H
D
I/O
(n+1)
External Address Blocked—Counter disabled (An + 1 reused)
X
X
An
↑
X
X
L
(4)
D
I/O
(0)
Counter Set to last valid
ADS
load
5626 tbl 03
相關(guān)PDF資料
PDF描述
IDT70V7599S200BF HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
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IDT70V7599S133BC HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
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