- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377397 > IDT72103L35J (INTEGRATED DEVICE TECHNOLOGY INC) CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 PDF資料下載
參數(shù)資料
| 型號： | IDT72103L35J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 |
| 中文描述： | 2K X 9 OTHER FIFO, 35 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 19/31頁 |
| 文件大小： | 314K |
| 代理商： | IDT72103L35J |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
5.37
19
enable and disable timings for
OE
are shown in Figure 12.
Single Device Mode
A single IDT172103/72104 may be used when application
requirements are for 2048/4096 words or less. The IDT72103/
72104 is in the Single Device Configuration when the Expan-
sion In (
Xl
) control input is grounded (See Figure 27). In this
mode, the
HF/XO
is used as a Half-Full flag.
Wldth Expanslon Mode
Word width may be increased simply by connecting the
corresponding input control signals of multiple devices. Sta-
tus flags can be detected from any one of the connected
devices. Figure 28 demonstrates an 18-bit word width by
using two IDT72103/72104s. Any word width can be attained
by adding additional IDT72103/72104.
OPERATING DESCRIPTION
PARALLEL OPERATING MODES:
Parallel Data Input
By setting
SI
/PI HIGH, data is written into the FIFO in
parallel through the D0-D8 input data lines.
Parallel Data Output
By setting
SO
/PO HIGH, the parallel-out mode is chosen.
In the parallel-out mode, as shown in Figure 4, data is
available tA after the falling edge of
R
and the output bus Q
goes into high-impedance after
R
goes HIGH.
Alternately, the user can access the FIFO by keeping
R
LOW and enabling data on the bus by asserting
OE
. When
R
is LOW, the
OE
is HIGH and the output bus is tri-stated. When
R
is HIGH, the output bus is disabled irrespective of
OE
. The
Figure 27. Block Diagram of Single 2048 x 9/4096 x 9 FIFO in Parallel Mode
2573 drw 30
IDT
72103/04
DATA
WRITE
FULL FLAG
FULL-MINUS-ONE
(W)
(D)
(FF)
(FF-1)
9
DATA
READ
EMPTY FLAG
EMPTY-PLUS-ONE
(R)
(Q)
(EF)
(EF+1)
9
HF
HALF-FULL FLAG
EXPANSION IN (XI)
OUT
IN
ALMOST FULL
(AEF)
RESET
(RS)
ALMOST EMPTY
(AEF)
RETRANSMIT
(RT)
OUPUT ENABLE
(OE)
(SI/PI)
(SO/PO)
V
CC
V
CC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72103L50J | CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 |
| IDT72104L50J | CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 |
| IDT72105 | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| IDT72105L25SO | Current-Mode PWM Controller 14-SOIC -40 to 85 |
| IDT72105L25TP | Current-Mode PWM Controller 8-SOIC -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72103S50P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72104S120P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72104S50D | 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:4K X 9 OTHER FIFO, 50 ns, CDIP40 |
| IDT72104S50P | 制造商:IDT/89'S 功能描述:FIFO, 4K x 9, Asynchronous, 40 Pin, Plastic, DIP |
| IDT72105L50S0 | 制造商:Integrated Device Technology Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。