參數(shù)資料
型號(hào)： IDT72103L35J
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
中文描述： 2K X 9 OTHER FIFO, 35 ns, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 21/31頁(yè)
文件大?。?/td> 314K
代理商： IDT72103L35J
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9
COMMERCIAL TEMPERATURE RANGES
5.37
21
NOTE:
1. Flag detection is accomplished by monitoring all the flag signals of either (any) device used in the width expansion configuration. Do not connect any
flag signals together.
Figure 28. Block Diagram of 2048 x 18/4096 x 18 FIFO Memory Used in Width Expansion in Parallel Mode
2753 drw 31
IDT
72103/04
DATA
WRITE
FULL FLAG
RESET
(W)
(D)
(FF)
(RS)
9
READ
EMPTY FLAG
RETRANSMIT
(R)
(EF)
(RT)
HF
(XI)
18
IDT
72103/04
HF
9
(XI)
9
9
(Q) DATA
18
OUT
IN
(SO/PO)
(SI/PI)
V
CC
(SI/PI)
(SO/PO)
V
CC
OUTPUT
ENABLE
(OE)
TRUTH TABLES
TABLE 2: RESET AND RETRANSMIT —
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION IN PARALLEL MODE
Inputs
(2)
Mode
RS
FL
XI
Reset
0
X
0
Retransmit
1
0
0
Read/Write
1
1
0
Internal Status
(1)
Outputs
FF
Read Pointer
Location Zero
Location Zero
Increment
(1)
Write Pointer
Location Zero
Unchanged
Increment
(1)
AEF
,
0
X
X
EF
HF
1
X
X
1
X
X
NOTES:
1. Pointer will increment if appropriate flag is HIGH.
2.
RS
= Reset Input,
FL
/
RT
= First Load/Retransmit,
EF
= Empty Flag Output,
2753 tbl 13
FF
= Full Flag Output,
XI
= Expansion Input.
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