參數(shù)資料
型號(hào)： IDT72103L35J
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
中文描述： 2K X 9 OTHER FIFO, 35 ns, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 24/31頁(yè)
文件大?。?/td> 314K
代理商： IDT72103L35J
5.37
24
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
COMMERCIAL TEMPERATURE RANGES
SERIAL OPERATING MODES:
Serial Data Input
The Serial Input mode is selected by grounding the Sl/PI
line. The D0-8 lines are then outputs which are used to
program the width of the serial word. They are taps off a digital
delay line which are meant for connection to the
W
input. For
instance, connecting D6 to
W
will program a serial word width
of 7 bits, connecting D7 to
W
will program a serial word width
of 8 bits and so on.
By programming the serial word width, an economy of
clock cycles is achieved. As an example, if the word width is
6 bits, then on every 6th clock cycle the serial data register is
written in parallel into the FIFO RAM array. Thus, the possible
clock cycles for an extra 3 bits of width in the RAM array are
not required.
The SIX signal is used for Serial-ln Expansion. When the
serial word width is 9 or less, the SIX input must be tied HIGH.
When more than 9 bits of serial word width is required, more
than one device is required. The SIX input of the least
significant device must be tied HIGH. The D8 pin of the least
significant device must be tied to SIX of the next significant
device. In other words, the SIX input of the most significant
and intermediate devices must always be connected to the D8
of the next least significant device.
Figure 32 shows the relationship of the SIX, SICP and D0-
8 lines. In the stand alone case (Figure 32), on the first LOW-
to-HlGH of SICP, the D1-8 lines go LOW and the D0 line
remains HIGH. On the next SICP clock edge, the D1 goes
HIGH, then D2 and so on. This continues until the D line, which
is connected to
W
, goes HIGH. On the next clock cycle, after
W
is HIGH, all of the D lines go LOW again and a new serial
word input starts.
In the cascaded case, the first LOW-to-HlGH SICP clock
edge for a serial word will cause all timed outputs (D) to go
LOW except for D0 of the least significant device. The D
outputs of the least significant device will go high on consecu-
tive clock cycles until D8. When D8 goes HlGH, the SlX of the
next device goes HlGH. On the next cycle after the SIX input
is brought HIGH, the D0 goes HIGH; then on the next cycle D1
and so on. A Di output from the most significant device is
issued to create the
W
for all cascaded devices.
The minimum serial word width is 4 bits and the maximum
is virtually unlimited.
When in the Serial mode, the Least Significant Bit of a serial
stream is shifted in first. If the FIFO output is in the Parallel
mode, the first serial bit will come out on Q0. The second bit
shifted in is on Q1 and so on.
In the Serial Cascade mode, the serial input (Sl) pins must
be connected together. Each of the devices then receives
serial information together and uses the SIX and D0-8 lines to
determine whether to store it or not.
The example shown in Figure 34 shows the interconnec-
tions for a serializing FIFO that transfers data to the internal
RAM in 16-bit quantities (i.e. every 16 SlCP cycles). This
corresponds to incrementing the write pointer every 16 SICP
cycles.
Once
W
goes HIGH With the last serial bit in, SICP should
not be clocked again until
FF
goes HIGH.
TABLE 3: RESET AND FIRST LOAD TRUTH TABLE —
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs
(2)
Mode
RS
FL
Reset-First
0
0
Device
Internal Status
Outputs
XI
Read Pointer
Write Pointer
EF
FF
(1)
Location Zero
Location Zero
0
1
Retransmit all
Other Devices
Read/Write
NOTES:
1.
XI
is connected to
XO
of previous device.
2.
RS
= Reset Input,
FL
/
RT
= First Load/Retransmit,
0
1
(1)
Location Zero
Location Zero
0
1
1
X
(1)
X
X
X
X
2753 tbl 14
EF
= Empty Flag Ouput,
FF
= Full Flag Output,
XI
= Expansion Input.
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