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參數(shù)資料
| 型號(hào)： | IDT72103L35J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 |
| 中文描述： | 2K X 9 OTHER FIFO, 35 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 4/31頁 |
| 文件大?。?/td> | 314K |
| 代理商： | IDT72103L35J |
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5.37
4
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION (Continued)
Symbol
Name
XO
/
HF
Expansion Out/
Half-Full Flag
I/O
O
Description
HF
is LOW when the FIFO is more than half-full in the single device or width expansion
modes. The
HF
will remain LOW until the difference between the write and read pointers is
less than or equal to one-half of the FIFO memory.
In depth expansion mode, a pulse is written from
XO
to
XI
of the next device when the last
location in the FIFO is filled. Another pulse is sent from
XO
to
Xl
of the next device when the
last FIFO location is read.
When
AEF
is LOW, the FIFO is empty to 1/8 full or 7/8 full to completely full. If
AEF
is HIGH,
then the FIFO is greater than 1/8 full, but less than 7/8 full.
AEF
Almost-Empty/
Almost-Full Flag
O
EF+1
Empty+1 Flag
Empty Flag
O
O
EF+ 1
is LOW when there is zero or one word word in the FIFO memory array.
EF
goes LOW when the FIFO is empty and further read operations are inhibited.
FF
is HIGH
when the FIFO is not empty and data reads are permitted.
Data input for serial data.
Data output for serial data.
EF
Sl
SO
Serial Input
Serial Output
I
O
SICP
Serial Input Clock
I
This pin is the serial input clock. On the rising edge of the SICP signal, new serial data bits
are read into the serial input shift register.
This pin is the serial output clock. On the rising edge of the SOCP signal, new serial data bits
are read from the serial output shift register.
SIX controls the serial input expansion for word widths greater than 9 bits. In a serial input
configuration, the SIX pin of the least significant device is tied HIGH. The SIX pin of all other
devices is connected to the D
8
pin of the previous device. In parallel input configurations or
serial input configurations of 9 bits or less, SIX is tied HIGH.
SOX controls the serial output expansion for word widths greater than 9 bits. In a serial output
configuration, the SOX pin of the least significant device is tied HIGH. The SOX pin of all other
devices is connected to the Q
8
pin of the previous device. In parallel output configurations
or serial output configurations of 9 bits or less, SOX is tied HIGH.
SOCP
Serial Output
Clock
I
SIX
Serial Input
Expansion
I
SOX
Serial Output
Expansion
I
SI
/PI
Serial/Parallel Input
I
When this pin is HIGH, the FIFO is in a parallel input configuration and accepts input data
through D
0
-D
8
. When
SI
/PI is LOW, the FIFO is in a serial input configuration and data is input
through Sl.
When this pin is HIGH, the FIFO is in a parallel output configuration and sends output data
through Q
0
-Q
8
. When
SO
/PO is LOW the FIFO is in a serial output configuration and data
is input through SO.
One ground pin for the DIP package and five ground pins for the LCC/PLCC packages.
One + 5V power pin.
SO
/PO
Serial/Parallel Output
I
GND
V
CC
Ground
Power
2753 tbl 05
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72103L50J | CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 |
| IDT72104L50J | CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 |
| IDT72105 | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| IDT72105L25SO | Current-Mode PWM Controller 14-SOIC -40 to 85 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72103S50P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72104S120P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72104S50D | 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:4K X 9 OTHER FIFO, 50 ns, CDIP40 |
| IDT72104S50P | 制造商:IDT/89'S 功能描述:FIFO, 4K x 9, Asynchronous, 40 Pin, Plastic, DIP |
| IDT72105L50S0 | 制造商:Integrated Device Technology Inc 功能描述: |
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