參數(shù)資料
型號: IDT72103L50J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
中文描述: 2K X 9 OTHER FIFO, 50 ns, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 12/31頁
文件大?。?/td> 314K
代理商: IDT72103L50J
5.37
12
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
COMMERCIAL TEMPERATURE RANGES
R
HF, FF-1
W
t
WF
2753 drw 13
t
RF
Figure 10. Half-Full and Full-minus-1 Flag Timings
R
EF+1
W
t
RE
2753 drw 14
t
WE
Figure 11. Empty+1 Flag Timings
2753 drw 15
OE
R
t
RC
t
RR
t
OELZ
DATA 1
DATA 1
t
DV
TERMINATE READ CYCLE
t
AOE
t
OEHZ
t
A
t
RLZ
SECOND READ BY CONTROLLING OE
Q
0-8
Figure 12. Output Enable Timings
2753 drw 16
W
R
XO
WRITE TO
LAST PHYSICAL
LOCATION
t
XOL
t
XOL
t
XOH
READ FROM
LAST PHYSICAL
LOCATION
t
XOH
Figure 13. Expansion-Out
相關(guān)PDF資料
PDF描述
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